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公开(公告)号：US07283419B2
公开(公告)日：2007-10-16
申请号：US11414554
申请日：2006-05-01
IPC分类号： G11C8/00
CPC分类号： G11C7/1045 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/408
摘要： An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.
摘要翻译： 集成半导体存储器件包括第一存储区，第二存储区，第一地址连接和第二地址连接。 存在于第二地址连接处的第二地址信号指定对第一或第二存储器区域的访问，而通过第一地址连接处的第一地址信号指定在第一或第二存储器区域内访问哪个存储器单元。 在第一存储器配置中，所有地址连接由地址信号从外部驱动，并且控制对第一或第二存储器区域中的存储器单元的访问。 在第二存储器配置中，仅第一地址连接从外部驱动，而模式寄存器中的信令位调节对第一或第二存储器区的访问。 即使不存在外部驱动第二地址连接的可能性，也可以访问第二存储区域。
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公开(公告)号：US20060277379A1
公开(公告)日：2006-12-07
申请号：US11414554
申请日：2006-05-01
CPC分类号： G11C7/1045 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/408
摘要： An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.
摘要翻译： 集成半导体存储器件包括第一存储区，第二存储区，第一地址连接和第二地址连接。 存在于第二地址连接处的第二地址信号指定对第一或第二存储器区域的访问，而通过第一地址连接处的第一地址信号指定在第一或第二存储器区域内访问哪个存储器单元。 在第一存储器配置中，所有地址连接由地址信号从外部驱动，并且控制对第一或第二存储器区域中的存储器单元的访问。 在第二存储器配置中，仅第一地址连接从外部驱动，而模式寄存器中的信令位调节对第一或第二存储器区的访问。 即使不存在外部驱动第二地址连接的可能性，也可以访问第二存储区域。
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3.发明授权公开(公告)号：US07154793B2
公开(公告)日：2006-12-26
申请号：US10948562
申请日：2004-09-24
IPC分类号： G11C29/06
CPC分类号： G11C7/18 , G11C29/34 , G11C2029/1204 , G11C2029/2602
摘要： An integrated memory includes memory cells arranged in a memory cell array along word lines and bit lines. One of the bit lines can be connected to a data line by a respective one of a plurality of switches. The memory contains column select lines. One of the column select lines in each case connected to a plurality of the switches for driving, in an activated state, in order to connect a number of bit lines to a same number of data lines. An access controller is connected to the column select lines and can be operated in a test operating mode such that a plurality of the column select lines are activated in the event of a memory cell access. The writing of test data to the memory cell array in a test operating mode can thus be optimized in accordance with the invention.
摘要翻译： 集成存储器包括沿着字线和位线布置在存储单元阵列中的存储器单元。 其中一个位线可以通过多个开关中的相应一个连接到数据线。 内存包含列选择行。 每种情况下的列选择线之一连接到多个开关，用于在激活状态下驱动，以将多个位线连接到相同数量的数据线。 访问控制器连接到列选择线，并且可以在测试操作模式下操作，使得在存储器单元访问的情况下多个列选择线被激活。 因此可以根据本发明优化将测试数据写入测试操作模式的存储单元阵列。
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4.发明授权公开(公告)号：US07102362B2
公开(公告)日：2006-09-05
申请号：US10920204
申请日：2004-08-18
IPC分类号： G01R27/06 , G01R31/3185 , G11C29/04
CPC分类号： G11C29/56 , G01R31/2884 , G11C11/401 , G11C29/48 , G11C2029/5602
摘要： An integrated circuit includes a first circuit component, a second circuit component, and an external terminal for making contact with the circuit. The first circuit component is connected to the external terminal via the second component. A bridging circuit connects the first circuit component to the external terminal and can be activated by a test mode signal. In the active state, the bridging circuit connects the external terminal to the first circuit component while bridging the second circuit component, while it is nonconducting in the deactivated state. Circuit components integrated in the semiconductor chip can be electrically measured nondestructively via activatable switches. Circuit components that lie between the external terminal and the device to be measured can be excluded from the measurement by bridging circuits. The method also makes it possible to measure a plurality of integrated devices in parallel or serially.
摘要翻译： 集成电路包括第一电路部件，第二电路部件和用于与电路接触的外部端子。 第一电路部件经由第二部件与外部端子连接。 桥接电路将第一电路组件连接到外部端子，并且可以通过测试模式信号来激活。 在激活状态下，桥接电路将外部端子连接到第一电路部件，同时桥接第二电路部件，同时其处于非导通状态。 集成在半导体芯片中的电路元件可以通过可激活开关非破坏性地电测量。 位于外部端子和待测量器件之间的电路元件可以通过桥接电路从测量中排除。 该方法还使得可以并行或串行地测量多个集成器件。
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5.发明授权公开(公告)号：US07180799B2
公开(公告)日：2007-02-20
申请号：US10948557
申请日：2004-09-24
IPC分类号： G11C7/00
CPC分类号： G11C7/1045
摘要： A circuit for setting one of a plurality of organization forms of an integrated circuit includes a detector circuit connected to an external connection of the integrated circuit. The external connection in at least one of the organization forms can be used for external communication of the integrated circuit. A signal can be impressed into a signal path connected to the external connection by the detector circuit. As a consequence, an output signal is generated at an output of the detector circuit. A control circuit sets one of the organization forms and receives the output signal of the detector circuit. One of the organization forms is set by the control circuit depending on the state of the output signal of the detector circuit. A module with a detector circuit can identify that organization form of the organization forms in which it is operated in the application.
摘要翻译： 用于设置集成电路的多个组织形式之一的电路包括连接到集成电路的外部连接的检测器电路。 组织形式中的至少一个的外部连接可用于集成电路的外部通信。 信号可以通过检测器电路加到连接到外部连接的信号路径中。 因此，在检测器电路的输出处产生输出信号。 控制电路设置组织形式之一并接收检测器电路的输出信号。 组织形式之一由控制电路根据检测器电路的输出信号的状态设置。 具有检测器电路的模块可以识别其在应用中操作的组织形式的组织形式。
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公开(公告)号：US20060187728A1
公开(公告)日：2006-08-24
申请号：US11238625
申请日：2005-09-29
申请人： Fabien Funfrock , Michael Sommer
发明人： Fabien Funfrock , Michael Sommer
IPC分类号： G11C7/00
CPC分类号： G11C29/021 , G11C7/12 , G11C11/401 , G11C11/4074 , G11C11/4094 , G11C29/028 , G11C29/50 , G11C2029/5006
摘要： An integrated semiconductor memory (100) comprises a controllable voltage generator (30) for precharging bit lines (BL) of a memory cell array (10) to a precharge voltage (VEQ). During the read-out of a first and second memory state of memory cells (SZ) which are connected to the bit lines, a first and second signal swing (ΔUH, ΔUL) occurs on the bit lines, as a result of which the bit lines are charged to a first and a second voltage potential (V1, V2). For the purpose of precharging the bit lines to the precharge voltage (VEQ), a first equalize current (I1) and a second equalize current (I2) are fed onto the bit lines by the controllable voltage generator (30), the current intensity of said currents in each case being measured by a detector circuit (60). A control circuit (20) alters the precharge voltage (VEQ) until the first and second equalize currents (I1, I2) have identical magnitudes. The precharge voltage is then centered with respect to the first and second voltage potentials (V1, V2).
摘要翻译： 集成半导体存储器（100）包括用于将存储单元阵列（10）的位线（BL）预充电到预充电电压（VEQ）的可控电压发生器（30）。 在连接到位线的存储单元（SZ）的第一和第二存储器状态的读出期间，在位线上出现第一和第二信号摆幅（DeltaUH，DeltaUL），结果是位 线路被充电到第一和第二电压电位（V 1，V 2）。 为了将位线预充电到预充电电压（VEQ），通过可控电压发生器（30）将第一均衡电流（I 1）和第二均衡电流（I 2）馈送到位线，电流 每种情况下所述电流的强度由检测器电路（60）测量。 控制电路（20）改变预充电电压（VEQ），直到第一和第二均衡电流（I 1，I 2）具有相同的幅度。 然后，预充电电压相对于第一和第二电压电位（V 1，V 2）居中。
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7.发明申请公开(公告)号：US20050040830A1
公开(公告)日：2005-02-24
申请号：US10920204
申请日：2004-08-18
申请人： Fabien Funfrock , Michael Sommer
发明人： Fabien Funfrock , Michael Sommer
CPC分类号： G11C29/56 , G01R31/2884 , G11C11/401 , G11C29/48 , G11C2029/5602
摘要： An integrated circuit includes a first circuit component, a second circuit component, and an external terminal for making contact with the circuit. The first circuit component is connected to the external terminal via the second component. A bridging circuit connects the first circuit component to the external terminal and can be activated by a test mode signal. In the active state, the bridging circuit connects the external terminal to the first circuit component while bridging the second circuit component, while it is nonconducting in the deactivated state. Circuit components integrated in the semiconductor chip can be electrically measured nondestructively via activatable switches. Circuit components that lie between the external terminal and the device to be measured can be excluded from the measurement by bridging circuits. The method also makes it possible to measure a plurality of integrated devices in parallel or serially.
摘要翻译： 集成电路包括第一电路部件，第二电路部件和用于与电路接触的外部端子。 第一电路部件经由第二部件与外部端子连接。 桥接电路将第一电路组件连接到外部端子，并且可以通过测试模式信号来激活。 在激活状态下，桥接电路将外部端子连接到第一电路部件，同时桥接第二电路部件，同时不导通处于去激活状态。 集成在半导体芯片中的电路元件可以通过可激活开关非破坏性地电测量。 位于外部端子和待测量器件之间的电路元件可以通过桥接电路从测量中排除。 该方法还使得可以并行或串行地测量多个集成器件。
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8.发明申请公开(公告)号：US20050068841A1
公开(公告)日：2005-03-31
申请号：US10948562
申请日：2004-09-24
申请人： Michael Sommer , Fabien Funfrock
发明人： Michael Sommer , Fabien Funfrock
CPC分类号： G11C7/18 , G11C29/34 , G11C2029/1204 , G11C2029/2602
摘要： An integrated memory includes memory cells arranged in a memory cell array along word lines and bit lines. One of the bit lines can be connected to a data line by a respective one of a plurality of switches. The memory contains column select lines. One of the column select lines in each case connected to a plurality of the switches for driving, in an activated state, in order to connect a number of bit lines to a same number of data lines. An access controller is connected to the column select lines and can be operated in a test operating mode such that a plurality of the column select lines are activated in the event of a memory cell access. The writing of test data to the memory cell array in a test operating mode can thus be optimized in accordance with the invention.
摘要翻译： 集成存储器包括沿着字线和位线布置在存储单元阵列中的存储器单元。 其中一个位线可以通过多个开关中的相应一个连接到数据线。 内存包含列选择行。 每种情况下的列选择线之一连接到多个开关，用于在激活状态下驱动，以便将多个位线连接到相同数量的数据线。 访问控制器连接到列选择线，并且可以在测试操作模式下操作，使得在存储器单元访问的情况下多个列选择线被激活。 因此可以根据本发明优化将测试数据写入测试操作模式的存储单元阵列。
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9.发明申请公开(公告)号：US20050068813A1
公开(公告)日：2005-03-31
申请号：US10948557
申请日：2004-09-24
申请人： Michael Sommer , Fabien Funfrock
发明人： Michael Sommer , Fabien Funfrock
IPC分类号： G11C7/00 , G11C7/10 , G11C11/4063
CPC分类号： G11C7/1045
摘要： A circuit for setting one of a plurality of organization forms of an integrated circuit comprises a detector circuit connected to an external connection of the integrated circuit. The external connection in at least one of the organization forms can be used for external communication of the integrated circuit. A signal can be impressed into a signal path connected to the external connection by the detector circuit. As a consequence, an output signal is generated at an output of the detector circuit. A control circuit sets one of the organization forms and receives the output signal of the detector circuit. One of the organization forms is set by the control circuit depending on the state of the output signal of the detector circuit. A module with a circuit according to the invention can identify that organization form of the organization forms in which it is operated in the application.
摘要翻译： 用于设置集成电路的多个组织形式之一的电路包括连接到集成电路的外部连接的检测器电路。 组织形式中的至少一个的外部连接可用于集成电路的外部通信。 信号可以通过检测器电路加到连接到外部连接的信号路径中。 因此，在检测器电路的输出处产生输出信号。 控制电路设置组织形式之一并接收检测器电路的输出信号。 组织形式之一由控制电路根据检测器电路的输出信号的状态设置。 具有根据本发明的电路的模块可以识别其在应用中操作的组织形式的组织形式。
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