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公开(公告)号：US07427202B2
公开(公告)日：2008-09-23
申请号：US11317638
申请日：2005-12-22
IPC分类号： H01R12/00
CPC分类号： H01R13/2407 , H01L23/49811 , H01L2224/81897 , H01L2924/0002 , H01L2924/3011 , H01R12/7041 , H01R13/627 , H05K3/305 , H05K3/325 , H05K3/4015 , H05K2201/0373 , H05K2201/10719 , H05K2201/209 , H01L2924/00
摘要： A means of attachment for electrically contacting electronic components is disclosed. The means of attachment includes a carrier element and a number of elongated connecting elements. Each of the connecting elements is arranged on the carrier element and has an elongated body, which protrudes from the carrier element. Each of the connecting elements and the carrier element includes an electrically conductive surface.
摘要翻译： 公开了一种用于电接触电子部件的连接装置。 附接装置包括载体元件和多个细长的连接元件。 每个连接元件布置在载体元件上并且具有从载体元件突出的细长主体。 每个连接元件和载体元件包括导电表面。
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公开(公告)号：US07355218B2
公开(公告)日：2008-04-08
申请号：US11202634
申请日：2005-08-12
IPC分类号： H01L27/10
CPC分类号： H01L27/092 , H01L21/765 , H01L21/823878
摘要： The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection or substrate connection.
摘要翻译： 对于相同的电导型，源极区域（3）像沟道区域一样被高度掺杂。 漏极区域（4）被掺杂用于相反的电导型。 这导致节省面积，因为源连接（S）可以同时用作阱连接或衬底连接。
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3.发明授权公开(公告)号：US07180799B2
公开(公告)日：2007-02-20
申请号：US10948557
申请日：2004-09-24
IPC分类号： G11C7/00
CPC分类号： G11C7/1045
摘要： A circuit for setting one of a plurality of organization forms of an integrated circuit includes a detector circuit connected to an external connection of the integrated circuit. The external connection in at least one of the organization forms can be used for external communication of the integrated circuit. A signal can be impressed into a signal path connected to the external connection by the detector circuit. As a consequence, an output signal is generated at an output of the detector circuit. A control circuit sets one of the organization forms and receives the output signal of the detector circuit. One of the organization forms is set by the control circuit depending on the state of the output signal of the detector circuit. A module with a detector circuit can identify that organization form of the organization forms in which it is operated in the application.
摘要翻译： 用于设置集成电路的多个组织形式之一的电路包括连接到集成电路的外部连接的检测器电路。 组织形式中的至少一个的外部连接可用于集成电路的外部通信。 信号可以通过检测器电路加到连接到外部连接的信号路径中。 因此，在检测器电路的输出处产生输出信号。 控制电路设置组织形式之一并接收检测器电路的输出信号。 组织形式之一由控制电路根据检测器电路的输出信号的状态设置。 具有检测器电路的模块可以识别其在应用中操作的组织形式的组织形式。
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4.发明授权Semiconductor chip with metallization levels, and a method for formation in interconnect structures 失效具有金属化水平的半导体芯片，以及在互连结构中形成的方法公开(公告)号：US07393721B2
公开(公告)日：2008-07-01
申请号：US11127782
申请日：2005-05-12
IPC分类号： H01L21/82
CPC分类号： H01L21/76892
摘要： A metallization surface (5), which acts as an etching stop layer during the production of openings (4) in a passivation layer (3) applied to its upper face and protects an interconnect structure (6) arranged underneath it, is arranged in an uppermost metallization level (1). A further opening is produced in the metal surface (5), through which a focused ion beam is aimed at the interconnect structure (6) in order to connect interconnects to one another and/or to interrupt at least one interconnect. The wiring of the integrated circuit can thus be varied individually, starting from identically produced semiconductor chips.
摘要翻译： 在施加到其上表面的钝化层（3）中制造开口（4）期间用作蚀刻停止层的金属化表面（5）并且保护布置在其下面的互连结构（6）被布置在 最高金属化水平（1）。 在金属表面（5）中产生进一步的开口，通过该开口，聚焦的离子束瞄准互连结构（6），以便将互连件彼此连接和/或中断至少一个互连。 因此，从相同制造的半导体芯片开始，集成电路的布线可以单独变化。
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公开(公告)号：US07317603B2
公开(公告)日：2008-01-08
申请号：US11389540
申请日：2006-03-27
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An integrated circuit with electrostatic discharge protection includes a first transistor with a source terminal, a drain terminal and a gate terminal, and a second transistor with a source terminal, a drain terminal and a gate terminal. The gate terminal for each of the first and second transistors is connected to the drain terminal. The first transistor is connected in series with the second transistor by one of the drain and source terminals of the first transistor being connected to one of the drain and source terminals of the second transistor. The series circuit formed by the transistors is connected to an input terminal of the integrated circuit or to a supply terminal and a terminal that applies the reference potential of the integrated circuit. The series circuit of the transistors is dimensioned by the number of transistors and the setting of the channel length and channel width ratios of the transistors.
摘要翻译： 具有静电放电保护的集成电路包括具有源极端子，漏极端子和栅极端子的第一晶体管以及具有源极端子，漏极端子和栅极端子的第二晶体管。 第一和第二晶体管中的每一个的栅极端子连接到漏极端子。 第一晶体管与第二晶体管串联连接，第一晶体管的漏极和源极之一连接到第二晶体管的漏极和源极端之一。 由晶体管形成的串联电路连接到集成电路的输入端子，或连接到施加集成电路的基准电位的电源端子和端子。 晶体管的串联电路由晶体管的数量和晶体管的沟道长度和沟道宽度比的设置来确定。
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公开(公告)号：US07283419B2
公开(公告)日：2007-10-16
申请号：US11414554
申请日：2006-05-01
IPC分类号： G11C8/00
CPC分类号： G11C7/1045 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/408
摘要： An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.
摘要翻译： 集成半导体存储器件包括第一存储区，第二存储区，第一地址连接和第二地址连接。 存在于第二地址连接处的第二地址信号指定对第一或第二存储器区域的访问，而通过第一地址连接处的第一地址信号指定在第一或第二存储器区域内访问哪个存储器单元。 在第一存储器配置中，所有地址连接由地址信号从外部驱动，并且控制对第一或第二存储器区域中的存储器单元的访问。 在第二存储器配置中，仅第一地址连接从外部驱动，而模式寄存器中的信令位调节对第一或第二存储器区的访问。 即使不存在外部驱动第二地址连接的可能性，也可以访问第二存储区域。
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公开(公告)号：US07279881B2
公开(公告)日：2007-10-09
申请号：US11218740
申请日：2005-09-06
IPC分类号： G05F3/24
CPC分类号： G05F1/618 , G11C5/147 , G11C11/4074
摘要： An integrated circuit includes a voltage generator with a first controllable resistor and a second controllable resistor, through which a first input terminal that applies a first voltage potential and a second input terminal that applies a second voltage potential can be connected to an output terminal that generates an output voltage. In a manner dependent on the output voltage, a first comparator circuit generates a first control signal to control the first controllable resistor, and a second comparator circuit generates a second control signal to control the second controllable resistor. A control unit evaluates the control signals generated by the comparator circuits and drives the first and second controllable resistors of the voltage generator in such a way that in each case only one of the two controllable resistors has a low-resistance state.
摘要翻译： 集成电路包括具有第一可控电阻器和第二可控电阻器的电压发生器，通过该电压发生器施加第一电压电位的第一输入端子和施加第二电压电位的第二输入端子可以连接到产生 输出电压。 以取决于输出电压的方式，第一比较器电路产生第一控制信号以控制第一可控电阻，第二比较器电路产生第二控制信号以控制第二可控电阻。 控制单元评估由比较器电路产生的控制信号，并驱动电压发生器的第一和第二可控电阻器，使得在每种情况下，两个可控电阻器中的仅一个具有低电阻状态。
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公开(公告)号：US07259607B2
公开(公告)日：2007-08-21
申请号：US11217676
申请日：2005-09-02
IPC分类号： G06F1/04
CPC分类号： H03K5/1252 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/084
摘要： An integrated semiconductor memory includes a clock generator circuit driven by an external clock signal and a control circuit driven by the external clock signal. The clock generator circuit generates an internal clock signal with a first level if the external clock signal level lies above a sensitivity level of the clock generator circuit for at least the duration of a sensitivity time of the clock generator circuit, and generates the internal clock signal with a second level if the external clock signal level lies below the sensitivity level for at least the duration of the sensitivity time of the clock generator circuit. The control circuit controls the clock generator circuit such that the control circuit selects the sensitivity time of the clock generator circuit in response to characteristics of the external clock signal.
摘要翻译： 集成半导体存储器包括由外部时钟信号驱动的时钟发生器电路和由外部时钟信号驱动的控制电路。 如果外部时钟信号电平在时钟发生器电路的灵敏度水平之上至少在时钟发生器电路的灵敏度时间的持续时间内，则时钟发生器电路产生具有第一电平的内部时钟信号，并且产生内部时钟信号 如果外部时钟信号电平至少在时钟发生器电路的灵敏度时间的持续时间内低于灵敏度电平，则具有第二电平。 控制电路控制时钟发生器电路，使得控制电路响应于外部时钟信号的特性来选择时钟发生器电路的灵敏度时间。
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9.发明授权公开(公告)号：US07102362B2
公开(公告)日：2006-09-05
申请号：US10920204
申请日：2004-08-18
IPC分类号： G01R27/06 , G01R31/3185 , G11C29/04
CPC分类号： G11C29/56 , G01R31/2884 , G11C11/401 , G11C29/48 , G11C2029/5602
摘要： An integrated circuit includes a first circuit component, a second circuit component, and an external terminal for making contact with the circuit. The first circuit component is connected to the external terminal via the second component. A bridging circuit connects the first circuit component to the external terminal and can be activated by a test mode signal. In the active state, the bridging circuit connects the external terminal to the first circuit component while bridging the second circuit component, while it is nonconducting in the deactivated state. Circuit components integrated in the semiconductor chip can be electrically measured nondestructively via activatable switches. Circuit components that lie between the external terminal and the device to be measured can be excluded from the measurement by bridging circuits. The method also makes it possible to measure a plurality of integrated devices in parallel or serially.
摘要翻译： 集成电路包括第一电路部件，第二电路部件和用于与电路接触的外部端子。 第一电路部件经由第二部件与外部端子连接。 桥接电路将第一电路组件连接到外部端子，并且可以通过测试模式信号来激活。 在激活状态下，桥接电路将外部端子连接到第一电路部件，同时桥接第二电路部件，同时其处于非导通状态。 集成在半导体芯片中的电路元件可以通过可激活开关非破坏性地电测量。 位于外部端子和待测量器件之间的电路元件可以通过桥接电路从测量中排除。 该方法还使得可以并行或串行地测量多个集成器件。
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10.发明授权公开(公告)号：US07002222B2
公开(公告)日：2006-02-21
申请号：US10753407
申请日：2004-01-09
IPC分类号： H01L29/76 , H01L29/90 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10873 , H01L21/823892 , H01L27/0207 , H01L27/108
摘要： An integrated semiconductor circuit, having active components lying in mutually adjoining wells of a respective first and second conduction type, wherein the active components respectively are associated with substrate contacts lying in direct proximity to an edge bounding the mutually adjoining wells, is disclosed. Preferably, structures of the active components other than the contacts are arranged to lie further away from the edge and the circuit/layout structures are not mirror-symmetrical with respect to a center line of the circuit chip.
摘要翻译： 公开了一种集成半导体电路，其具有位于相应的第一和第二导电类型的相互邻接的阱中的有源部件，其中所述有源部件分别与位于邻近所述相互邻接的阱的边缘直接接近的衬底接触相关联。 优选地，除了触点之外的有源部件的结构布置成更远离边缘，并且电路/布局结构相对于电路芯片的中心线不是镜像对称的。
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