Invention Grant
- Patent Title: Phase locked loop circuit
- Patent Title (中): 锁相环电路
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Application No.: US11202266Application Date: 2005-08-12
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Publication No.: US07301405B2Publication Date: 2007-11-27
- Inventor: Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
- Applicant: Manabu Kawabe , Kazuyuki Hori , Satoshi Tanaka , Yukinori Akamine , Masumi Kasahara , Kazuo Watanabe
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Reed Smith LLP
- Agent Stanley P. Fisher, Esq.; Juan Carlos A. Marquez, Esq.
- Priority: JP2004-262875 20040909
- Main IPC: H03L7/00
- IPC: H03L7/00

Abstract:
The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.
Public/Granted literature
- US20060049878A1 Phase locked loop circuit Public/Granted day:2006-03-09
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