公开(公告)号：US20060121858A1

公开(公告)日：2006-06-08

申请号：US11207003

申请日：2005-08-19

申请人： Satoshi Tanaka ,  Kazuyuki Hori ,  Manabu Kawabe ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

发明人： Satoshi Tanaka ,  Kazuyuki Hori ,  Manabu Kawabe ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

IPC分类号： H04B1/40 ,  H04B1/02

CPC分类号： H04B1/406 ,  H04B1/0003

摘要： A ΣΔ transmitter that permits setting of a loop filter LF, a charge pump current and other factors to the same conditions even if it is operated in a plurality of frequency bands, therefore allows the number of components to be reduced and at the same time enables the angle between the phases of local signals for reception use to be close to exactly 90°, which is a feature ensuring robustness against inter-element variations and accordingly suitable for large scale integration, is to be provided. The oscillation frequency of a VCO is set to an even-number multiple of the transmit frequency, and generates transmit signals via a divider. A device that varies the gain according to the amplitude component of modulating signals is added to an amplifier whose input is signals from the VCO, and the transmission of modulating signals involving amplitude modulation, such as EDGE, is thereby made possible.

摘要翻译： 即使在多个频带中工作的情况下，也可以将环路滤波器LF，电荷泵电流和其他因素设定为相同条件的SigmaDelta发送器，因此允许部件数量减少，同时使能 要提供用于接收的本地信号的相位之间的角度接近正好90°，这是确保对元件间变化的鲁棒性并因此适合于大规模集成的特征。 将VCO的振荡频率设定为发送频率的偶数倍，经由分频器生成发送信号。 根据调制信号的幅度分量来改变增益的装置被添加到其输入是来自VCO的信号的放大器，并且由此使得涉及幅度调制（例如EDGE）的调制信号的传输成为可能。

公开(公告)号：US07800452B2

公开(公告)日：2010-09-21

申请号：US11976408

申请日：2007-10-24

申请人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

发明人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

IPC分类号： H03L7/00

CPC分类号： H03L7/107 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/0991 ,  H03L7/1974 ,  H03L7/1976

摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation.This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

摘要翻译： 本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。 该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块 预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。 基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

公开(公告)号：US20080061890A1

公开(公告)日：2008-03-13

申请号：US11976408

申请日：2007-10-24

申请人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

发明人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

IPC分类号： H03L7/00

CPC分类号： H03L7/107 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/0991 ,  H03L7/1974 ,  H03L7/1976

摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

摘要翻译： 本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。 该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块 预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。 基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

公开(公告)号：US07426377B2

公开(公告)日：2008-09-16

申请号：US11207003

申请日：2005-08-19

申请人： Satoshi Tanaka ,  Kazuyuki Hori ,  Manabu Kawabe ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

发明人： Satoshi Tanaka ,  Kazuyuki Hori ,  Manabu Kawabe ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

IPC分类号： H04B1/06

CPC分类号： H04B1/406 ,  H04B1/0003

摘要： A ΣΔ transmitter that permits setting of a loop filter LF, a charge pump current and other factors to the same conditions even if it is operated in a plurality of frequency bands, therefore allows the number of components to be reduced and at the same time enables the angle between the phases of local signals for reception use to be close to exactly 90°, which is a feature ensuring robustness against inter-element variations and accordingly suitable for large scale integration, is to be provided. The oscillation frequency of a VCO is set to an even-number multiple of the transmit frequency, and generates transmit signals via a divider. A device that varies the gain according to the amplitude component of modulating signals is added to an amplifier whose input is signals from the VCO, and the transmission of modulating signals involving amplitude modulation, such as EDGE, is thereby made possible.

摘要翻译： 即使在多个频带中工作的情况下，也可以将环路滤波器LF，电荷泵电流和其他因素设定为相同条件的SigmaDelta发送器，因此允许减少部件的数量，并且同时启用 要提供用于接收的本地信号的相位之间的角度接近正好90°，这是确保对元件间变化的鲁棒性并因此适合于大规模集成的特征。 将VCO的振荡频率设定为发送频率的偶数倍，经由分频器生成发送信号。 根据调制信号的幅度分量来改变增益的装置被添加到其输入是来自VCO的信号的放大器，并且由此使得涉及幅度调制（例如EDGE）的调制信号的传输成为可能。

公开(公告)号：US07301405B2

公开(公告)日：2007-11-27

申请号：US11202266

申请日：2005-08-12

申请人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

发明人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

IPC分类号： H03L7/00

CPC分类号： H03L7/107 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/0991 ,  H03L7/1974 ,  H03L7/1976

摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

摘要翻译： 本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。 该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块 预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。 基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

公开(公告)号：US20060049878A1

公开(公告)日：2006-03-09

申请号：US11202266

申请日：2005-08-12

申请人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

发明人： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

IPC分类号： H03L7/00

CPC分类号： H03L7/107 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/0991 ,  H03L7/1974 ,  H03L7/1976

摘要： The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

摘要翻译： 本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。 该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块 预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。 基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

公开(公告)号：US07366489B2

公开(公告)日：2008-04-29

申请号：US10742813

申请日：2003-12-23

申请人： Satoshi Tanaka ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

发明人： Satoshi Tanaka ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

IPC分类号： H04B1/06 ,  H04B1/10

CPC分类号： H04B1/30 ,  H03D2200/0047 ,  H03K21/16

摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

摘要翻译： 适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。 此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。 每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。 另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除 消除。

公开(公告)号：US07224948B1

公开(公告)日：2007-05-29

申请号：US10148960

申请日：2000-01-11

申请人： Taizo Yamawaki ,  Satoshi Tanaka ,  Masaru Kokubo ,  Kazuo Watanabe ,  Masumi Kasahara ,  Kazuaki Hori ,  Julian Hildersley

发明人： Taizo Yamawaki ,  Satoshi Tanaka ,  Masaru Kokubo ,  Kazuo Watanabe ,  Masumi Kasahara ,  Kazuaki Hori ,  Julian Hildersley

IPC分类号： H04B1/04 ,  H01Q11/12

CPC分类号： H03C3/0983 ,  H03C3/0925 ,  H03C3/0966 ,  H03D7/163 ,  H03J2200/17 ,  H03L7/23 ,  H04B1/0475 ,  H04B2001/0491 ,  H04L25/03343

摘要： There are provided a transmitter and a wireless communication terminal apparatus using the same for solving a problem of undesired spurs due to harmonics of an output signal of a frequency synthesizer, and further solving a problem of the undesired spurs occurring when the harmonics of an output signal of a crystal oscillator are mixed into a VCO to facilitate to design a circuit or a mounting substrate. The transmitter has a relationship between an output frequency of a PLL frequency conversion circuit (5) and output frequencies of frequency synthesizers (1, 2) stored therein, and the output frequencies of the frequency synthesizers (1, 2) input into the PLL frequency conversion circuit (5) are controlled on the basis of the relationship so that the undesired spurs are suppressed. Thereby, even when the undesired spurs occur in the output of the transmitter due to a crosstalk between circuits or through a substrate, which can be easily suppressed, it is therefore possible to reduce time and cost for redesigning the circuit or the substrate.

摘要翻译： 提供了一种使用该发送器和无线通信终端装置的方法，用于解决由于频率合成器的输出信号的谐波引起的不期望的杂散问题，并且进一步解决了当输出信号的谐波发生时出现的不需要的杂散的问题 的晶体振荡器混合到VCO中以便于设计电路或安装衬底。 发射机具有PLL频率转换电路（5）的输出频率和存储在其中的频率合成器（1,2）的输出频率与输入到PLL频率的频率合成器（1,2）的输出频率之间的关系 基于该关系来控制转换电路（5），从而抑制不需要的杂散。 因此，即使由于电路之间的串扰或通过可以容易地抑制的基板而在发射机的输出端发生不想要的杂散，因此可以减少重新设计电路或基板的时间和成本。

公开(公告)号：US07885626B2

公开(公告)日：2011-02-08

申请号：US12056576

申请日：2008-03-27

申请人： Satoshi Tanaka ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

发明人： Satoshi Tanaka ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

IPC分类号： H04B1/06 ,  H04B1/10

CPC分类号： H04B1/30 ,  H03D2200/0047 ,  H03K21/16

摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

摘要翻译： 适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。 此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。 每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。 另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除 消除。

公开(公告)号：US06826388B1

公开(公告)日：2004-11-30

申请号：US09711105

申请日：2000-11-14

申请人： Satoshi Tanaka ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

发明人： Satoshi Tanaka ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

IPC分类号： H04B140

CPC分类号： H04B1/30 ,  H03D2200/0047 ,  H03K21/16

摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

摘要翻译： 适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。 此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。 每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。 另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除 消除。