发明授权
US07308669B2 Use of redundant routes to increase the yield and reliability of a VLSI layout
有权
使用冗余路由来提高VLSI布局的收益和可靠性
- 专利标题: Use of redundant routes to increase the yield and reliability of a VLSI layout
- 专利标题(中): 使用冗余路由来提高VLSI布局的收益和可靠性
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申请号: US10908593申请日: 2005-05-18
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公开(公告)号: US07308669B2公开(公告)日: 2007-12-11
- 发明人: Markus T. Buehler , John M. Cohn , David J. Hathaway , Jason D. Hibbeler , Juergen Koehl
- 申请人: Markus T. Buehler , John M. Cohn , David J. Hathaway , Jason D. Hibbeler , Juergen Koehl
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Gibb & Rahman, LLC
- 代理商 Richard M. Kotulak, Esq.
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.
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