发明授权
US07339235B1 Semiconductor device having SOI structure and manufacturing method thereof
失效
具有SOI结构的半导体器件及其制造方法
- 专利标题: Semiconductor device having SOI structure and manufacturing method thereof
- 专利标题(中): 具有SOI结构的半导体器件及其制造方法
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申请号: US09635832申请日: 2000-08-09
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公开(公告)号: US07339235B1公开(公告)日: 2008-03-04
- 发明人: Shunpei Yamazaki , Hisashi Ohtani , Jun Koyama , Takeshi Fukunaga
- 申请人: Shunpei Yamazaki , Hisashi Ohtani , Jun Koyama , Takeshi Fukunaga
- 申请人地址: JP Atsugi-shi, Kanagawa-ken
- 专利权人: Semiconductor Energy Laboratory Co., Ltd.
- 当前专利权人: Semiconductor Energy Laboratory Co., Ltd.
- 当前专利权人地址: JP Atsugi-shi, Kanagawa-ken
- 代理机构: Fish & Richardson P.C.
- 优先权: JP8-269215 19960918
- 主分类号: H01L29/76
- IPC分类号: H01L29/76 ; H01L29/94
摘要:
A fine semiconductor device having a short channel length while suppressing a short channel effect. Linearly patterned or dot-patterned impurity regions 104 are formed in a channel forming region 103 so as to be generally parallel with the channel direction. The impurity regions 104 are effective in suppressing the short channel effects. More specifically, the impurity regions 104 suppress expansion of a drain-side depletion layer, so that the punch-through phenomenon can be prevented. Further, the impurity regions cause a narrow channel effect, so that reduction in threshold voltage can be lessened.
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