发明授权
- 专利标题： PLL with controlled VCO bias
- 专利标题（中）： 具有受控VCO偏置的PLL
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申请号： US11218207申请日： 2005-08-31
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公开(公告)号： US07342426B2公开(公告)日： 2008-03-11
- 发明人: Nasser A. Kurd , Javed S. Barkatullah
- 申请人： Nasser A. Kurd , Javed S. Barkatullah
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 主分类号： H03L7/06
- IPC分类号： H03L7/06
摘要：
In some embodiments, a PLL with an output to provide a PLL output clock at a target frequency is provided. The PLL comprises a VCO to generate a clock to be used to generate the PLL output clock. Also provided is circuitry to maintain the VCO's bias level at a sufficient level if it is insufficient. Other embodiments may be disclosed herein.
公开/授权文献
- US20070046343A1 PLL with controlled VCO bias 公开/授权日：2007-03-01
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