发明授权
US07348827B2 Apparatus and methods for adjusting performance of programmable logic devices
有权
用于调节可编程逻辑器件性能的装置和方法
- 专利标题： Apparatus and methods for adjusting performance of programmable logic devices
- 专利标题（中）： 用于调节可编程逻辑器件性能的装置和方法
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申请号： US10848953申请日： 2004-05-19
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公开(公告)号： US07348827B2公开(公告)日： 2008-03-25
- 发明人: Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
- 申请人： Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Law Offices of Maximilian R. Peterson
- 主分类号： G05F3/02
- IPC分类号： G05F3/02
摘要：
A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).
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