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    Apparatus and methods for adjusting performance of programmable logic devices
    1.
    发明授权
    Apparatus and methods for adjusting performance of programmable logic devices 有权
    用于调节可编程逻辑器件性能的装置和方法

    公开(公告)号：US07348827B2

    公开(公告)日：2008-03-25

    申请号：US10848953

    申请日：2004-05-19

    申请人： Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

    发明人： Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

    IPC分类号： G05F3/02

    CPC分类号： H03K19/1731 ,  G06F17/5054 ,  H03K19/00369 ,  H03K2217/0018

    摘要： A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

    摘要翻译： 可编程逻辑器件（PLD）包括用于调整或设置一个或多个晶体管的体偏置的机构。 PLD包括体偏置发生器。 体偏置发生器被配置为设置可编程逻辑器件内的一个或多个晶体管的体偏置。 更具体地，体偏置发生器设置晶体管的体偏置，以便折衷晶体管的性能和功耗。

    Electrical fuse with sacrificial contact
    3.
    发明授权
    Electrical fuse with sacrificial contact 失效
    电熔丝与牺牲接触

    公开(公告)号：US07759226B1

    公开(公告)日：2010-07-20

    申请号：US11216682

    申请日：2005-08-30

    申请人： Shih-Lin S. Lee ,  Richard Smolen ,  Peter Mcelheny ,  Christopher Pass

    发明人： Shih-Lin S. Lee ,  Richard Smolen ,  Peter Mcelheny ,  Christopher Pass

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The electrical fuse includes a cathode pad, an anode pad and a fuse link connecting the cathode pad to the anode pad. The cathode pad includes a group of multiple electrical contacts and a solitary electrical contact disposed a predetermined distance from the group and near the fuse link, i.e., between the group of multiple electrical contacts and the fuse link. The cathode and anode pads as well as the fuse link include a polysilicon layer and a silicide layer.

    摘要翻译： 电熔丝包括阴极焊盘，阳极焊盘和将阴极焊盘连接到阳极焊盘的熔断体。 阴极焊盘包括一组多个电触头和一组独立的电触头，该绝缘电触点设置在距组件和熔丝连接点附近预定距离处，即在多组电触头组和熔断体之间。 阴极和阳极焊盘以及熔断体包括多晶硅层和硅化物层。

    On-chip voltage regulator using feedback on process/product parameters
    5.
    发明授权
    On-chip voltage regulator using feedback on process/product parameters 有权
    片上电压调节器，使用过程/产品参数反馈

    公开(公告)号：US07170308B1

    公开(公告)日：2007-01-30

    申请号：US10628711

    申请日：2003-07-28

    申请人： Irfan Rahim ,  Peter McElheny ,  John Costello

    发明人： Irfan Rahim ,  Peter McElheny ,  John Costello

    IPC分类号： G01R31/00 ,  G01R31/28 ,  G05F1/00

    CPC分类号： G11C5/147 ,  H03K19/177

    摘要： The present invention optimizes the performance of integrated circuits by adjusting the circuit operating voltage using feedback on process/product parameters. To determine a desired value for the operating voltage of an integrated circuit, a preferred embodiment provides for on-wafer probing of one or more reference circuit structures to measure at least one electrical or operational parameter of the one or more reference circuit structures; determining an adjusted value for the operating voltage based on the measured parameter; and establishing the adjusted value as the desired value for the operating voltage. The reference circuit structures may comprise process control monitor structures or structures in other integrated circuits fabricated in the same production run. In an alternative embodiment, the one or more parameters are directly measured from the integrated circuit whose operating voltage is being adjusted.

    摘要翻译： 本发明通过使用对过程/产品参数的反馈来调节电路工作电压来优化集成电路的性能。 为了确定集成电路的工作电压的期望值，优选实施例提供一个或多个参考电路结构的片上探测，以测量一个或多个参考电路结构的至少一个电或操作参数; 基于所测量的参数确定所述工作电压的调整值; 并将调整后的值建立为工作电压的期望值。 参考电路结构可以包括在相同生产运行中制造的其它集成电路中的过程控制监视器结构或结构。 在替代实施例中，一个或多个参数是直接从其工作电压正被调整的集成电路测量的。

    Method for implementing electro-static discharge protection in silicon-on-insulator devices
    8.
    发明授权
    Method for implementing electro-static discharge protection in silicon-on-insulator devices 失效
    在绝缘体上硅器件中实施静电放电保护的方法

    公开(公告)号：US06906387B1

    公开(公告)日：2005-06-14

    申请号：US10687420

    申请日：2003-10-15

    申请人： Dirk Alan Reese ,  Peter McElheny ,  Minchang Liang

    发明人： Dirk Alan Reese ,  Peter McElheny ,  Minchang Liang

    IPC分类号： H01L23/62 ,  H01L27/02

    CPC分类号： H01L27/0266

    摘要： The present invention is a method and apparatus whereby two NMOS or PMOS devices connected in a stacked gate configuration formed on SOI exhibit improved ESD response characteristics. The shared source-drain region between the two devices is formed to have a dopant depth in the shared region that does not extend through the silicon layer to the BOX layer. This provides a common body for the two devices, and thus a single parasitic bipolar transistor is formed between the drain of one NMOS or PMOS device and the source of the second NMOS or PMOS device. Simultaneous snapback occurs for the two devices through the common body. A further embodiment includes a method of forming two or more stacked gate NMOS or PMOS devices on SOI. The method includes protecting the shared source-drain region between two NMOS or PMOS devices during a final doping step and silicide processing.

    摘要翻译： 本发明是一种方法和装置，其中在SOI上形成的堆叠栅极配置中连接的两个NMOS或PMOS器件表现出改进的ESD响应特性。 两个器件之间的共享源极 - 漏极区域形成为在共享区域中具有不延伸穿过硅层到BOX层的掺杂剂深度。 这为两个器件提供了一个共同体，因此在一个NMOS或PMOS器件的漏极和第二个NMOS或PMOS器件的源极之间形成单个寄生双极晶体管。 两台设备通过通用主机同时发生回跳。 另一实施例包括在SOI上形成两个或多个层叠栅极NMOS或PMOS器件的方法。 该方法包括在最终掺杂步骤和硅化物处理期间保护两个NMOS或PMOS器件之间的共享源极 - 漏极区域。

    Polysilicon gate doping level variation for reduced leakage current
    10.
    发明授权
    Polysilicon gate doping level variation for reduced leakage current 有权
    多晶硅栅掺杂电平变化，减少漏电流

    公开(公告)号：US06750106B2

    公开(公告)日：2004-06-15

    申请号：US10156267

    申请日：2002-05-28

    申请人： Peter McElheny ,  Priya Selvaraj ,  Bill Liu ,  Francois Gregoire

    发明人： Peter McElheny ,  Priya Selvaraj ,  Bill Liu ,  Francois Gregoire

    IPC分类号： H01L218234

    CPC分类号： H01L21/823842

    摘要： A method of fabricating transistors on a semiconductor substrate is disclosed according to a first embodiment of the present invention. Gate dielectrics of equal thickness are provided to a first and second transistor on the semiconductor substrate. A polysilicon doping level of the first transistor is varied with a polysilicon doping level of the second transistor.

    摘要翻译： 根据本发明的第一实施例公开了一种在半导体衬底上制造晶体管的方法。 相同厚度的栅极电介质被提供给半导体衬底上的第一和第二晶体管。 第一晶体管的多晶硅掺杂水平随着第二晶体管的多晶硅掺杂水平而变化。