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    Apparatus and methods for adjusting performance of programmable logic devices
    2.
    发明授权
    Apparatus and methods for adjusting performance of programmable logic devices 有权
    用于调节可编程逻辑器件性能的装置和方法

    公开(公告)号：US07348827B2

    公开(公告)日：2008-03-25

    申请号：US10848953

    申请日：2004-05-19

    申请人： Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

    发明人： Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

    IPC分类号： G05F3/02

    CPC分类号： H03K19/1731 ,  G06F17/5054 ,  H03K19/00369 ,  H03K2217/0018

    摘要： A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

    摘要翻译： 可编程逻辑器件（PLD）包括用于调整或设置一个或多个晶体管的体偏置的机构。 PLD包括体偏置发生器。 体偏置发生器被配置为设置可编程逻辑器件内的一个或多个晶体管的体偏置。 更具体地，体偏置发生器设置晶体管的体偏置，以便折衷晶体管的性能和功耗。

    Method for electronically measuring size of internal void in electrically conductive lead
    3.
    发明授权
    Method for electronically measuring size of internal void in electrically conductive lead 失效
    用于电子测量导电铅内部空隙尺寸的方法

    公开(公告)号：US06242924B1

    公开(公告)日：2001-06-05

    申请号：US09236844

    申请日：1999-01-25

    申请人： Tsui Ting Yiu ,  Yow Juang W. Liu ,  Young-Chang Joo ,  Sunil N. Shabde

    发明人： Tsui Ting Yiu ,  Yow Juang W. Liu ,  Young-Chang Joo ,  Sunil N. Shabde

    IPC分类号： H01H3102

    CPC分类号： G01N27/20

    摘要： The size of an internal void in an electrically conductive lead is measured by determining its electrical resistance at a plurality of A.C. frequencies, ranging from D.C. to a frequency on the order of 50 to 100 GHz at which the majority of current flows along the skin of the lead. The test data is compared with reference data for an electrically conductive reference lead having characteristics which are essentially similar to the test lead. The difference between the two sets of data increases with the size of an internal void in the test lead. The difference will be greatest at D.C. because the current will flow through substantially the entire cross-section of the lead and the cross-sectional area will be reduced by the internal void. The test data will approach the reference data as the frequency increases because the majority of the current will flow through the skin of the test lead and will be less affected by the internal void. The surface roughness of a lead caused by surface voids is measured by determining its electrical resistance at a frequency high enough that the majority of the current flows through the skin of the lead. The distance at which the surface current flows, and thereby the resistance of the lead, increase with the surface roughness.

    摘要翻译： 通过确定其在多个AC频率处的电阻来测量导电引线中的内部空隙的尺寸，其范围从DC到大约50至100GHz的频率，其中大部分电流沿着皮肤 带头。 将测试数据与具有与测试引线基本相似的特性的导电参考引线的参考数据进行比较。 两组数据之间的差异随测试引线内部空隙的大小而增加。 差异在直流电中将最大，因为电流将大部分流过导线的整个横截面，横截面积将由内部空隙减小。 随着频率增加，测试数据将接近参考数据，因为大部分电流将流过测试导线的皮肤，并且将受到内部空隙的影响较小。 由表面空隙引起的铅的表面粗糙度通过以足够高的频率确定其电阻来测量，使得大部分电流流过铅的皮肤。 表面电流流动的距离，从而引线的电阻随着表面粗糙度的增加而增加。

    Apparatus and methods for multi-gate silicon-on-insulator transistors
    4.
    发明授权
    Apparatus and methods for multi-gate silicon-on-insulator transistors 有权
    多栅极绝缘体上硅晶体管的装置和方法

    公开(公告)号：US07415690B2

    公开(公告)日：2008-08-19

    申请号：US11930105

    申请日：2007-10-31

    申请人： Minchang Liang ,  Yow-Juang W. Liu

    发明人： Minchang Liang ,  Yow-Juang W. Liu

    IPC分类号： H03K17/693

    CPC分类号： G06F17/5054 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78648 ,  H03K17/6871 ,  H03K17/693 ,  H03K2217/0018

    摘要： An integrated circuit (IC) includes mechanisms for adjusting or setting the gate bias of one gate of one or more multi-gate transistors. The IC includes a gate bias generator. The gate bias generator is configured to set gate bias of one gate of the one or more multi-gate transistors within the IC. More specifically, the gate bias generator sets the gate bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

    摘要翻译： 集成电路（IC）包括用于调整或设置一个或多个多栅极晶体管的一个栅极的栅极偏置的机构。 IC包括栅极偏置发生器。 栅极偏置发生器被配置为设置IC内的一个或多个多栅极晶体管的一个栅极的栅极偏置。 更具体地，栅极偏置发生器设置晶体管的栅极偏置，以便折衷晶体管的性能和功耗。

    Integrated circuits with reduced standby power consumption
    5.
    发明授权
    Integrated circuits with reduced standby power consumption 有权
    具有降低待机功耗的集成电路

    公开(公告)号：US06940307B1

    公开(公告)日：2005-09-06

    申请号：US10691756

    申请日：2003-10-22

    申请人： Yow-Juang W. Liu ,  Hugh O ,  Richard G. Cliff

    发明人： Yow-Juang W. Liu ,  Hugh O ,  Richard G. Cliff

    IPC分类号： H03K19/00 ,  H03K19/173

    CPC分类号： H03K19/0016

    摘要： Integrated circuit standby power consumption may be reduced using a reverse-bias transistor control arrangement that reduces transistor leakage current. Integrated circuit transistors may be turned off using a reverse bias voltage rather than a ground voltage. A charge pump circuit on the integrated circuit may be used to generate the reverse bias voltage. The reverse bias voltage may also be provided from an external source. The integrated circuit may be a programmable logic device in which logic is configured by providing programming data to configuration cells. The configuration cells may be used to apply either a positive power supply voltage to a given transistor to turn that transistor on or to provide the reverse bias voltage to that transistor to turn that transistor off.

    摘要翻译： 可以使用降低晶体管漏电流的反向偏置晶体管控制装置来降低集成电路待机功耗。 集成电路晶体管可以使用反向偏置电压而不是接地电压来关断。 可以使用集成电路上的电荷泵电路来产生反向偏置电压。 也可以从外部源提供反向偏置电压。 集成电路可以是可编程逻辑器件，其中通过向配置单元提供编程数据来配置逻辑。 配置单元可以用于将正电源电压施加到给定晶体管以将该晶体管导通，或者向该晶体管提供反向偏置电压以将该晶体管截止。

    Integrated circuits with reduced standby power consumption
    9.
    发明授权
    Integrated circuits with reduced standby power consumption 有权
    具有降低待机功耗的集成电路

    公开(公告)号：US07109748B1

    公开(公告)日：2006-09-19

    申请号：US11147759

    申请日：2005-06-07

    申请人： Yow-Juang W Liu ,  Hugh Sungki O ,  Richard G Cliff

    发明人： Yow-Juang W Liu ,  Hugh Sungki O ,  Richard G Cliff

    IPC分类号： H03K19/173

    CPC分类号： H03K19/0016

    摘要： Integrated circuit standby power consumption may be reduced using a reverse-bias transistor control arrangement that reduces transistor leakage current. Integrated circuit transistors may be turned off using a reverse bias voltage rather than a ground voltage. A charge pump circuit on the integrated circuit may be used to generate the reverse bias voltage. The reverse bias voltage may also be provided from an external source. The integrated circuit may be a programmable logic device in which logic is configured by providing programming data to configuration cells. The configuration cells may be used to apply either a positive power supply voltage to a given transistor to turn that transistor on or to provide the reverse bias voltage to that transistor to turn that transistor off.

    摘要翻译： 可以使用降低晶体管漏电流的反向偏置晶体管控制装置来降低集成电路待机功耗。 集成电路晶体管可以使用反向偏置电压而不是接地电压来关断。 可以使用集成电路上的电荷泵电路来产生反向偏置电压。 也可以从外部源提供反向偏置电压。 集成电路可以是可编程逻辑器件，其中通过向配置单元提供编程数据来配置逻辑。 配置单元可以用于将正电源电压施加到给定晶体管以将该晶体管导通，或者向该晶体管提供反向偏置电压以将该晶体管截止。