Invention Grant
- Patent Title: Self-synchronising bit error analyser and circuit
- Patent Title (中): 自同步位误差分析器和电路
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Application No.: US11164690Application Date: 2005-12-01
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Publication No.: US07404115B2Publication Date: 2008-07-22
- Inventor: Gerard Boudon , Didier Malcavet , David Pereira , Andre Steimle
- Applicant: Gerard Boudon , Didier Malcavet , David Pereira , Andre Steimle
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Joseph P. Abate; Daryl Neff
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.
Public/Granted literature
- US20070011534A1 SELF-SYNCHRONISING BIT ERROR ANALYSER AND CIRCUIT Public/Granted day:2007-01-11
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