公开(公告)号：US07404115B2

公开(公告)日：2008-07-22

申请号：US11164690

申请日：2005-12-01

Applicant: Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

Inventor： Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

IPC: G01R31/28

CPC classification number: G01R31/3171

Abstract: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract translation: 一种自同步数据总线分析器，包括发生器LFSR，接收器LFSR和比较器，其中发生器LFSR产生通过数据总线传送到比较器的第一数据组; 并且其中所述比较器将所述第一数据集与由所述接收器LFSR生成的第二数据集进行比较，并且调整所述接收器LFSR，直到所述第二数据集与所述第一数据集基本相同。

公开(公告)号：US5463574A

公开(公告)日：1995-10-31

申请号：US99119

申请日：1993-07-29

Applicant: Bernard Desrosiers ,  Didier Louis ,  Didier Pinchon ,  Andre Steimle

Inventor： Bernard Desrosiers ,  Didier Louis ,  Didier Pinchon ,  Andre Steimle

IPC: G06F7/556 ,  G06F7/38

CPC classification number: G06F7/556 ,  G06F7/49947

Abstract: An apparatus for executing argument reduction in the computation of F(x)=2**x-1 (with .vertline.x.vertline.

Abstract translation: 一种用于在F（x）= 2 ** x-1（具有| x | <1）的计算中执行参数减少的装置，根据IEEE 754标准浮点型确定xi的值和计算（x-xi） 点格式具有第一电路装置，其可操作以对N位尾数执行流水线操作; 第一电路装置的输出连接到N + 4位的归一化电路，其三个最左边的输入被连接到“零”，并且其三个最左边的位J（0：2） 位总线（J-BUS）。 还包括一个领先的零检测器/编码器电路和第二电路装置，其可操作用于对输出控制对准器电路的编码器电路的指数执行流水线操作，以及由检测器/编码器电路和编码器电路的输出驱动的选择器电路 其输出控制归一化电路; xi确定电路，其在连接到第一电路装置的xi-BUS上产生xi尾数，使得：尾数xi = 0 = K（1）K（2）1 0。 。 。 ，以及用于存储F（xi）值的只读存储器，其输出连接到用于F（xi）的相应尾数和指数部分的第一和第二电路的输入。

公开(公告)号：US5621863A

公开(公告)日：1997-04-15

申请号：US481591

申请日：1995-06-07

Applicant: Jean-Yves Boulet ,  Didier Louis ,  Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

Inventor： Jean-Yves Boulet ,  Didier Louis ,  Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

IPC: G06F15/18 ,  G06K9/66 ,  G06N3/00 ,  G06N3/06 ,  G06N3/063 ,  G06N3/08

CPC classification number: G06K9/6272 ,  G06K9/00986 ,  G06N3/063

Abstract: In a neural network comprised of a plurality of neuron circuits, an improved neuron circuit that generates local result signals, e.g. of the fire type, and a local output signal of the distance or category type. The neuron circuit which is connected to buses that transport input data (e.g. the input category) and control signals. A multi-norm distance evaluation circuit calculates the distance D between the input vector and a prototype vector stored in a R/W memory circuit. A distance compare circuit compares this distance D with either the stored prototype vector's actual influence field or the lower limit thereof to generate first and second comparison signals. An identification circuit processes the comparison signals, the input category signal, the local category signal and a feedback signal to generate local result signals that represent the neuron circuit's response to the input vector. A minimum distance determination circuit determines the minimum distance Dmin among all the calculated distances from all of the neuron circuits of the neural network and generates a local output signal of the distance type. The circuit may be used to search and sort categories. The feed-back signal is collectively generated by all the neuron circuits by ORing all the local distances/categories. A daisy chain circuit is serially connected to corresponding daisy chain circuits of two adjacent neuron circuits to chain the neurons together. The daisy chain circuit also determines the neuron circuit state as free or engaged. Finally, a context circuitry enables or inhibits neuron participation with other neuron circuits in generation of the feedback signal.

Abstract translation: 在由多个神经元电路组成的神经网络中，生成本地结果信号的改进的神经元电路，例如， 的火灾类型，以及距离或类别类型的本地输出信号。 连接到传送输入数据（例如输入类别）和控制信号的总线的神经元电路。 多范围距离评估电路计算输入矢量和存储在R / W存储器电路中的原型矢量之间的距离D. 距离比较电路将该距离D与存储的原型矢量的实际影响场或其下限进行比较，以产生第一和第二比较信号。 识别电路处理比较信号，输入类别信号，局部类别信号和反馈信号，以产生表示神经元电路对输入矢量的响应的本地结果信号。 最小距离确定电路确定来自神经网络的所有神经元电路的所有计算距离中的最小距离Dmin，并产生距离类型的局部输出信号。 该电路可用于搜索和分类。 所有的神经元电路通过对所有的局部距离/类别进行OR运算来共同地产生反馈信号。 菊花链电路串联连接到两个相邻神经元电路的相应菊花链电路，以将神经元链接在一起。 菊花链电路还将神经元电路状态确定为自由或接合。 最后，上下文电路在反馈信号的产生中实现或抑制与其他神经元电路的神经元参与。

公开(公告)号：US07661039B2

公开(公告)日：2010-02-09

申请号：US12154188

申请日：2008-05-21

Applicant: Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

Inventor： Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

IPC: G06F11/00

CPC classification number: G01R31/3171

Abstract: A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract translation: 提供了一种自同步数据总线分析器，其可以包括发生器线性反馈移位寄存器（LFSR）以产生第一数据集，并且可以包括接收器LFSR以生成第二数据集。 数据总线分析器还可以包括比特采样器，以对通过耦合到发生器LFSR的数据总线接收的第一数据集进行采样，并输出采样的第一数据集。 可以包括比较器以将采样的第一数据集与由接收机LFSR生成的第二数据集进行比较，并向接收机LFSR提供信号以调整接收机LFSR的相位，直到第二数据组与第一数据集基本相同 数据集。

公开(公告)号：US06377941B1

公开(公告)日：2002-04-23

申请号：US09338450

申请日：1999-06-22

Applicant: Andre Steimle ,  Pascal Tannhof

Inventor： Andre Steimle ,  Pascal Tannhof

IPC: G06F1518

CPC classification number: G06K9/6271 ,  G06N3/063 ,  G06N3/08

Abstract: A method of achieving automatic learning of an input vector presented to an artificial neural network (ANN) formed by a plurality of neurons, using the K nearest neighbor (KNN) mode. Upon providing an input vector to be learned to the ANN, a Write component operation is performed to store the input vector components in the first available free neuron of the ANN. Then, a Write category operation is performed by assigning a category defined by the user to the input vector. Next, a test is performed to determine whether this category matches the categories of the nearest prototypes, i.e. which are located at the minimum distance. If it matches, this first free neuron is not engaged. Otherwise, it is engaged by assigning the matching category to it. As a result, the input vector becomes the new prototype with the matching category associated thereto. Further described is a circuit which automatically retains the first free neuron of the ANN for learning.

Abstract translation: 使用K个最近邻（KNN）模式，实现由多个神经元形成的人造神经网络（ANN）的输入向量的自动学习的方法。 在向ANN提供要学习的输入向量时，执行写分量操作以将输入矢量分量存储在ANN的第一可用游离神经元中。 然后，通过将由用户定义的类别分配给输入向量来执行写类别操作。 接下来，执行测试以确定该类别是否与最近的原型的类别匹配，即位于最小距离的类别。 如果它匹配，这个第一个自由神经元没有被使用。 否则，通过将匹配类别分配给它来进行。 结果，输入向量成为与其相关联的匹配类别的新原型。 进一步描述了自动保留ANN的第一自由神经元进行学习的电路。

公开(公告)号：US5701397A

公开(公告)日：1997-12-23

申请号：US485336

申请日：1995-06-07

Applicant: Andre Steimle ,  Didier Louis ,  Guy Paillet

Inventor： Andre Steimle ,  Didier Louis ,  Guy Paillet

IPC: G06F15/18 ,  G06N3/00 ,  G06N3/04 ,  G06N3/06 ,  G06N3/063

CPC classification number: G06K9/6271 ,  G06K9/00986 ,  G06N3/063

Abstract: In each neuron in a neural network of a plurality of neuron circuits either in an engaged or a free state, a pre-charge circuit, that allows loading the components of an input vector (A) only into a determined free neuron circuit during a recognition phase as a potential prototype vector (B) attached to the determined neuron circuit. The pre-charge circuit is a weight memory (251) controlled by a memory control signal (RS) and the circuit generating the memory control signal. The memory control signal identifies the determined free neuron circuit. During the recognition phase, the memory control signal is active only for the determined free neuron circuit. When the neural network is a chain of neuron circuits, the determined free neuron circuit is the first free neuron in the chain. The input vector components on an input data bus (DATA-BUS) are connected to the weight memory of all neuron circuits. The data therefrom are available in each neuron on an output data bus (RAM-BUS). The pre-charge circuit may further include an address counter (252) for addressing the weight memory and a register (253) to latch the data output on the output data bus. After the determined neuron circuit has been engaged, the contents of its weight memory cannot be modified. Pre-charging the input vector during the recognition phase makes the engagement process more efficient and significantly reduces learning time in learning the input vector.

Abstract translation: 在接合或自由状态下的多个神经元电路的神经网络中的每个神经元中，预充电电路允许在识别期间将输入矢量（A）的分量加载到确定的自由神经元电路中 相作为附着到确定的神经元电路的潜在原型载体（B）。 预充电电路是由存储器控制信号（RS）控制的重量存储器（251）和产生存储器控制信号的电路。 存储器控制信号识别确定的自由神经元电路。 在识别阶段期间，存储器控制信号仅对所确定的自由神经元电路有效。 当神经网络是神经元电路链时，确定的游离神经元电路是链中的第一个游离神经元。 输入数据总线（DATA-BUS）上的输入向量分量连接到所有神经元电路的权重存储器。 其数据可在输出数据总线（RAM-BUS）上的每个神经元中使用。 预充电电路还可以包括用于寻址权重存储器的地址计数器（252）和用于锁存输出数据总线上的数据的寄存器（253）。 在确定的神经元电路被接合之后，其重量记忆的内容不能被修改。 在识别阶段对输入向量进行预充电，使得参与过程更有效，并显着减少学习输入向量的学习时间。

公开(公告)号：US20090019326A1

公开(公告)日：2009-01-15

申请号：US12154188

申请日：2008-05-21

Applicant: Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

Inventor： Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

IPC: G06F11/00

CPC classification number: G01R31/3171

Abstract: A self-synchronizing data bus analyser is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract translation: 提供了一种自同步数据总线分析器，其可以包括发生器线性反馈移位寄存器（LFSR）以产生第一数据集，并且可以包括接收器LFSR以生成第二数据集。 数据总线分析器还可以包括比特采样器，以对通过耦合到发生器LFSR的数据总线接收的第一数据集进行采样，并输出采样的第一数据集。 可以包括比较器以将采样的第一数据集与由接收机LFSR生成的第二数据集进行比较，并向接收机LFSR提供信号以调整接收机LFSR的相位，直到第二数据组与第一数据集基本相同 数据集。

公开(公告)号：US20050212932A1

公开(公告)日：2005-09-29

申请号：US10906333

申请日：2005-02-15

Applicant: Andre Steimle ,  Bernard Jung

Inventor： Andre Steimle ,  Bernard Jung

IPC: G06F1/32 ,  H04N5/374 ,  H04N9/64

CPC classification number: H04N5/23241 ,  H04N5/335

Abstract: The image sensing device interface unit attached to an image sensing device has dedicated means to detect a complete missing line and to perform clock gating of circuits for power management self-optimization. For each image frame, the time interval between start of line 1 and start of line 2 is computed and stored in a first register. The time interval between any other pair of two consecutive lines is also computed and stored in a second register. The stored values are compared, and if the value in the second register is greater than in the first register, a complete missing line has been detected and the gated clock used in said circuits is switched off for power saving. The interface unit can adapt to any type of sensor and does not require the help of any processor to perform the power saving function.

Abstract translation: 附加到图像感测装置的图像感测装置接口单元具有专用装置，用于检测完整的缺失线并执行用于电源管理自优化的电路的时钟选通。 对于每个图像帧，计算行1开始和行2开始之间的时间间隔并将其存储在第一寄存器中。 任何其他两对连续行之间的时间间隔也被计算并存储在第二寄存器中。 比较存储的值，并且如果第二寄存器中的值大于第一寄存器中的值，则检测到完整的缺失行，并且在所述电路中使用的门控时钟被关闭以进行省电。 接口单元可以适应任何类型的传感器，并且不需要任何处理器的帮助来执行省电功能。

公开(公告)号：US06535862B1

公开(公告)日：2003-03-18

申请号：US09411289

申请日：1999-10-04

Applicant: Didier Louis ,  Andre Steimle

Inventor： Didier Louis ,  Andre Steimle

IPC: G06N302

CPC classification number: G06K9/6271 ,  G06K9/6262 ,  G06N3/063

Abstract: A diagnostic method engages all the neurons of an artificial neural network (ANN) based on mapping an input space defined by vector components based on category, context, and actual field of influence (AIF). The method includes the steps loading the components of a first and second input vectors into the ANN; engaging all the neurons of a same prototype; having all the neurons compute their own distance between the respective prototypes and the second input vector (which should be the same if the neurons were good); determining the minimum distance Dmin and comparing Dmin with a distance D measured between the first and the second input vectors. If Dmin

Abstract translation: 基于对基于类别，上下文和实际影响领域（AIF）的矢量分量定义的输入空间的映射，诊断方法接合人造神经网络（ANN）的所有神经元。 该方法包括将第一和第二输入向量的分量加载到ANN中的步骤; 吸引同一原型的所有神经元; 所有的神经元都计算它们自己在各个原型之间的距离和第二个输入向量（如果神经元是好的，它们应该相同）; 确定最小距离Dmin并将Dmin与在第一和第二输入向量之间测量的距离D进行比较。 如果Dmin = D，ANN的良好神经元被取消选择，防止良好的神经元进一步学习/识别处理; 并重复前面的步骤直到ANN为空。 本方法提供了以仅仅几个逻辑门为代价的形成ANN的神经元的快速廉价的完整性诊断。

公开(公告)号：US5717832A

公开(公告)日：1998-02-10

申请号：US488443

申请日：1995-06-07

Applicant: Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

Inventor： Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

IPC: G06F15/18 ,  G06N3/00 ,  G06N3/04 ,  G06N3/06 ,  G06N3/063 ,  G06E1/00

CPC classification number: G06K9/00986 ,  G06K9/6271 ,  G06N3/063

Abstract: A base neural semiconductor chip (10) including a neural network or unit (11(#)). The neural network (11(#)) has a plurality of neuron circuits fed by different buses transporting data such as the input vector data, set-up parameters, and control signals. Each neuron circuit (11) includes logic for generating local result signals of the "fire" type (F) and a local output signal (NOUT) of the distance or category type on respective buses (NR-BUS, NOUT-BUS). An OR circuit (12) performs an OR function for all corresponding local result and output signals to generate respective first global result (R*) and output (OUT*) signals on respective buses (R*-BUS, OUT*-BUS) that are merged in an on-chip common communication bus (COM*-BUS) shared by all neuron circuits of the chip. In a multi-chip network, an additional OR function is performed between all corresponding first global result and output signals (which are intermediate signals) to generate second global result (R**) and output (OUT**) signals, preferably by dotting onto an off-chip common communication bus (COM**-BUS) in the chip's driver block (19). This latter bus is shared by all the base neural network chips that are connected to it in order to incorporate a neural network of the desired size. In the chip, a multiplexer (21) may select either the intermediate output or the global output signal to be fed back to all neuron circuits of the neural network, depending on whether the chip is used in a single or multi-chip environment via a feed-back bus (OR-BUS). The feedback signal is the result of a collective processing of all the local output signals.

Abstract translation: 一种包括神经网络或单元（11（＃））的基本神经半导体芯片（10）。 神经网络（11（＃））具有由不同总线馈送的多个神经元电路，其传送诸如输入矢量数据，设置参数和控制信号的数据。 每个神经元电路（11）包括用于在相应总线（NR-BUS，NOUT-BUS）上产生“火”类型（F）的本地结果信号和距离或类别类型的本地输出信号（NOUT）的逻辑。 OR电路（12）对所有对应的本地结果和输出信号执行OR功能，以在相应总线（R * -BUS，OUT * -BUS）上产生相应的第一全局结果（R *）和输出（OUT *）信号， 被合并在由芯片的所有神经元电路共享的片上公共通信总线（COM * -BUS）中。 在多芯片网络中，在所有对应的第一全局结果和输出信号（它们是中间信号）之间执行附加OR功能，以产生第二全局结果（R **）和输出（OUT **）信号，优选地通过点划线 在芯片的驱动器块（19）中的片外公共通信总线（COM ** - BUS）上。 该后一个总线由连接到它的所有基本神经网络芯片共享以便并入所需大小的神经网络。 在芯片中，多路复用器（21）可以选择要反馈给神经网络的所有神经元电路的中间输出或全局输出信号，这取决于芯片是经由单芯片还是多芯片环境使用 反馈总线（OR-BUS）。 反馈信号是对所有局部输出信号的集中处理的结果。