Self-synchronising bit error analyser and circuit
    1.
    发明授权
    Self-synchronising bit error analyser and circuit 失效
    自同步位误差分析器和电路

    公开(公告)号:US07404115B2

    公开(公告)日:2008-07-22

    申请号:US11164690

    申请日:2005-12-01

    IPC分类号: G01R31/28

    CPC分类号: G01R31/3171

    摘要: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

    摘要翻译: 一种自同步数据总线分析器,包括发生器LFSR,接收器LFSR和比较器,其中发生器LFSR产生通过数据总线传送到比较器的第一数据组; 并且其中所述比较器将所述第一数据集与由所述接收器LFSR生成的第二数据集进行比较,并且调整所述接收器LFSR,直到所述第二数据集与所述第一数据集基本相同。

    SELF-SYNCHRONISING BIT ERROR ANALYSER AND CIRCUIT
    2.
    发明申请
    SELF-SYNCHRONISING BIT ERROR ANALYSER AND CIRCUIT 失效
    自同步位错误分析器和电路

    公开(公告)号:US20070011534A1

    公开(公告)日:2007-01-11

    申请号:US11164690

    申请日:2005-12-01

    IPC分类号: G01R31/28

    CPC分类号: G01R31/3171

    摘要: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

    摘要翻译: 一种自同步数据总线分析器,包括发生器LFSR,接收器LFSR和比较器,其中发生器LFSR产生通过数据总线传送到比较器的第一数据组; 并且其中所述比较器将所述第一数据集与由所述接收器LFSR生成的第二数据集进行比较,并且调整所述接收器LFSR,直到所述第二数据集与所述第一数据集基本相同。

    Self-synchronizing bit error analyzer and circuit
    3.
    发明申请
    Self-synchronizing bit error analyzer and circuit 失效
    自同步位误差分析器和电路

    公开(公告)号:US20090019326A1

    公开(公告)日:2009-01-15

    申请号:US12154188

    申请日:2008-05-21

    IPC分类号: G06F11/00

    CPC分类号: G01R31/3171

    摘要: A self-synchronizing data bus analyser is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

    摘要翻译: 提供了一种自同步数据总线分析器,其可以包括发生器线性反馈移位寄存器(LFSR)以产生第一数据集,并且可以包括接收器LFSR以生成第二数据集。 数据总线分析器还可以包括比特采样器,以对通过耦合到发生器LFSR的数据总线接收的第一数据集进行采样,并输出采样的第一数据集。 可以包括比较器以将采样的第一数据集与由接收机LFSR生成的第二数据集进行比较,并向接收机LFSR提供信号以调整接收机LFSR的相位,直到第二数据组与第一数据集基本相同 数据集。

    Self-synchronizing bit error analyzer and circuit
    4.
    发明授权
    Self-synchronizing bit error analyzer and circuit 失效
    自同步位误差分析器和电路

    公开(公告)号:US07661039B2

    公开(公告)日:2010-02-09

    申请号:US12154188

    申请日:2008-05-21

    IPC分类号: G06F11/00

    CPC分类号: G01R31/3171

    摘要: A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

    摘要翻译: 提供了一种自同步数据总线分析器,其可以包括发生器线性反馈移位寄存器(LFSR)以产生第一数据集,并且可以包括接收器LFSR以生成第二数据集。 数据总线分析器还可以包括比特采样器,以对通过耦合到发生器LFSR的数据总线接收的第一数据集进行采样,并输出采样的第一数据集。 可以包括比较器以将采样的第一数据集与由接收机LFSR生成的第二数据集进行比较,并向接收机LFSR提供信号以调整接收机LFSR的相位,直到第二数据组与第一数据集基本相同 数据集。

    Electric power supply circuit for a turbojet engine nacelle
    5.
    发明授权
    Electric power supply circuit for a turbojet engine nacelle 有权
    涡轮喷气发动机舱的电源电路

    公开(公告)号:US08777155B2

    公开(公告)日:2014-07-15

    申请号:US13384807

    申请日:2010-06-29

    IPC分类号: B64D41/00

    摘要: The present invention relates to an electric power supply circuit (1) for a turbojet engine nacelle including at least one electric generator (2) mechanically connected to the shaft of a turbojet engine, said generator being capable of directly supplying electric power to a first electric power device other than a simple monitoring or supervising unit, characterized in that said generator is capable of directly supplying electric power to at least one second electric power device other than a monitoring or supervising unit, as well as to a nacelle including such an electric circuit.

    摘要翻译: 本发明涉及一种用于涡轮喷气发动机机舱的电力供应回路(1),其包括机械地连接到涡轮喷气发动机的轴的至少一个发电机(2),所述发电机能够直接向第一电动机 除了简单的监视或监督单元之外的功率装置,其特征在于,所述发电机能够直接向除了监视或监督单元之外的至少一个第二电力装置提供电力,以及包括这种电路的机舱 。

    System for controlling the cowl of a turbojet engine nacelle thrust reverser
    8.
    发明授权
    System for controlling the cowl of a turbojet engine nacelle thrust reverser 有权
    用于控制涡轮喷气发动机机舱推力反向器的整流罩的系统

    公开(公告)号:US08939401B2

    公开(公告)日:2015-01-27

    申请号:US12867432

    申请日:2008-11-21

    IPC分类号: F02K1/32 F02K1/76

    CPC分类号: F02K1/763 Y02T50/671

    摘要: A nacelle for a turbojet engine includes an air inlet forward section, a median section surrounding a fan of the turbojet engine, an aft section equipped with a thrust reverser system, a power control unit able to convert a high voltage electric supply into an electric supply towards an electromechanical actuator, and a drive unit for the power control unit which is distinct and separate from the latter and has a control input and a drive output to be connected to the power control unit. The thrust reverser system includes a mobile cowl which, under action of an electromechanical actuator, is able to move from a closed position to an open position in which the mobile cowl opens a passage in the nacelle.

    摘要翻译: 用于涡轮喷气发动机的机舱包括进气前进部分,围绕涡轮喷气发动机的风扇的中间部分,配备有推力反向器系统的后部部分,能够将高压电源转换成电力供应的动力控制单元 朝向机电致动器,以及用于功率控制单元的驱动单元,其与后者不同且分离,并具有要连接到功率控制单元的控制输入和驱动输出。 推力反向器系统包括移动整流罩,其在机电致动器的作用下能够从关闭位置移动到打开位置,在该位置移动导管打开机舱中的通道。

    AIRCRAFT ENGINE NACELLE COMPRISING A MOBILE COWL MOVED BY ELECTRIC MOTORS
    9.
    发明申请
    AIRCRAFT ENGINE NACELLE COMPRISING A MOBILE COWL MOVED BY ELECTRIC MOTORS 有权
    包含电动机移动的移动机的飞机发动机

    公开(公告)号:US20120107109A1

    公开(公告)日:2012-05-03

    申请号:US13320360

    申请日:2010-05-19

    IPC分类号: F01D25/24

    摘要: A nacelle for receiving an aircraft engine, the nacelle having a tubular stationary cover and at least one movable portion connected to the stationary cover via movement means for moving the movable portion between a position close to the stationary cover and a position spaced apart therefrom. The movement means have asynchronous motors, each having a stator with windings connected in parallel to a power supply circuit and a rotor having windings, each connected to a resistive load in parallel with a winding of the rotor of each of the other motors.

    摘要翻译: 一种用于接收飞机发动机的机舱,所述机舱具有管状固定盖和经由移动装置连接到所述固定盖的至少一个可移动部分,用于在靠近所述固定盖的位置和与所述固定盖间隔开的位置之间移动所述可动部。 移动装置具有异步电动机,每个异步电动机具有定子,其绕组与电源电路并联连接,绕组具有绕组,每个转子与每个其它电动机的转子的绕组并联连接到电阻负载。

    Circuit for bit alignment in high speed multichannel data transmission
    10.
    发明授权
    Circuit for bit alignment in high speed multichannel data transmission 失效
    电路用于高速多通道数据传输中的位对齐

    公开(公告)号:US07606341B2

    公开(公告)日:2009-10-20

    申请号:US10710046

    申请日:2004-06-15

    申请人: David Pereira

    发明人: David Pereira

    IPC分类号: H04L7/00 H04L25/00 H04L25/40

    摘要: An alignment circuit is configured to receive a reference clock signal (ref_clk) derived from a main clock having a period T and successive sets of 2n data bits that are transmitted in parallel on a data bus wherein said data bits are aligned with respect to said reference clock signal but misaligned with respect to each other. It first comprises a plurality of n aligners. Each aligner is coupled to said reference clock and a pair of said data bits, referred to as primary bits, one data bit (bit_tdat(i)) having the rank (i) in a determined set and the other being the corresponding data bit (bit_tdat(i+n)) having the rank (i+n) in the set. Each aligner comprises first, second and third shifting means for shifting said primary data bits to respectively generate respective data bits delayed of one, two and two and half cycles and a multiplexor receiving said primary and delayed data bits under the control of three control signals of a first type (recal(i), realign0(i) and realign1(i)) to generate a pair of aligned data bits (tdat_desk(i) & tdat_desk(i+n)).

    摘要翻译: 对准电路被配置为接收从具有周期T的主时钟导出的参考时钟信号(ref_clk)和在数据总线上并行发送的2n个数据位的连续组,其中所述数据位相对于所述参考 时钟信号,但彼此不对齐。 它首先包括多个n个对准器。 每个对准器耦合到所述参考时钟和被称为主要位的一对所述数据位,所述数据位在确定的集合中具有秩(i)的一个数据位(bit_tdat(i)),另一个是对应的数据位 bit_tdat(i + n))在集合中具有秩(i + n)。 每个对准器包括第一,第二和第三移位装置,用于移位所述主数据位以分别产生延迟一个,两个和两个和两个周期的相应数据位;以及多路复用器,在三个控制信号的控制下接收所述主要和延迟数据位 第一类型(recal(i),realign0(i)和realign1(i))以产生一对对齐的数据位(tdat_desk(i)&tdat_desk(i + n))。