Invention Grant
US07454639B2 Various apparatuses and methods for reduced power states in system memory
有权
用于在系统存储器中降低功率状态的各种装置和方法
- Patent Title: Various apparatuses and methods for reduced power states in system memory
- Patent Title (中): 用于在系统存储器中降低功率状态的各种装置和方法
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Application No.: US11174060Application Date: 2005-06-30
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Publication No.: US07454639B2Publication Date: 2008-11-18
- Inventor: Sandeep Jain , James P. Kardach
- Applicant: Sandeep Jain , James P. Kardach
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F1/26 ; G06F1/32

Abstract:
A method, apparatus, and system are described in which a memory controller may have two or more registers to create and track zones of memory in a volatile memory device. The memory controller controls a power consumption state of a first zone of memory in the volatile memory device and a second zone of memory within the first volatile memory device on an individual basis; and one or more memory arrays contained within the first volatile memory device.
Public/Granted literature
- US20070005998A1 Various apparatuses and methods for reduced power states in system memory Public/Granted day:2007-01-04
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