发明授权
- 专利标题: Strategy to verify asynchronous links across chips
- 专利标题(中): 跨芯片验证异步链接的策略
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申请号: US10815903申请日: 2004-03-31
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公开(公告)号: US07464287B2公开(公告)日: 2008-12-09
- 发明人: Debendra Das Sharma , Gurushankar Rajamani , Hanh Hoang
- 申请人: Debendra Das Sharma , Gurushankar Rajamani , Hanh Hoang
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: G06F5/06
- IPC分类号: G06F5/06 ; G06F17/50 ; G06F7/62
摘要:
Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.
公开/授权文献
- US20050220121A1 Strategy to verify asynchronous links across chips 公开/授权日:2005-10-06
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