发明授权
US07498217B2 Methods of manufacturing semiconductor memory devices with unit cells having charge trapping layers
失效
制造具有电荷捕获层的单元电池的半导体存储器件的方法
- 专利标题: Methods of manufacturing semiconductor memory devices with unit cells having charge trapping layers
- 专利标题(中): 制造具有电荷捕获层的单元电池的半导体存储器件的方法
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申请号: US11746761申请日: 2007-05-10
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公开(公告)号: US07498217B2公开(公告)日: 2009-03-03
- 发明人: Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Woo-Gwan Shim , Jong-Won Lee
- 申请人: Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Woo-Gwan Shim , Jong-Won Lee
- 申请人地址: KR
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR
- 代理机构: Myers Bigel Sibley & Sajovec
- 优先权: KR10-2006-0043035 20060512
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238 ; H01L21/8242 ; H01L21/336
摘要:
In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is formed on the first layer. The preliminary second layer pattern has an upper face substantially lower than or substantially equal to an upper face of the isolation layer. A third layer is formed on the preliminary second layer and the isolation layer. A fourth layer is formed on the third layer. The fourth layer, the third layer, the preliminary second layer pattern and the first layer are partially etched to form a gate structure on the substrate. Source/drain regions are formed at portions of the substrate adjacent to the gate structure.