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    Methods of manufacturing semiconductor memory devices with unit cells having charge trapping layers
    1.
    发明授权
    Methods of manufacturing semiconductor memory devices with unit cells having charge trapping layers 失效
    制造具有电荷捕获层的单元电池的半导体存储器件的方法

    公开(公告)号：US07498217B2

    公开(公告)日：2009-03-03

    申请号：US11746761

    申请日：2007-05-10

    申请人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Woo-Gwan Shim ,  Jong-Won Lee

    发明人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Woo-Gwan Shim ,  Jong-Won Lee

    IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L21/336

    CPC分类号： H01L27/115 ,  H01L21/76229 ,  H01L27/11568

    摘要： In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is formed on the first layer. The preliminary second layer pattern has an upper face substantially lower than or substantially equal to an upper face of the isolation layer. A third layer is formed on the preliminary second layer and the isolation layer. A fourth layer is formed on the third layer. The fourth layer, the third layer, the preliminary second layer pattern and the first layer are partially etched to form a gate structure on the substrate. Source/drain regions are formed at portions of the substrate adjacent to the gate structure.

    摘要翻译： 在制造诸如SONOS型半导体器件的半导体器件的方法中，在衬底上形成沟槽。 形成从衬底突出的隔离层以填充沟槽。 在基板上形成第一层之后，在第一层上形成预备的第二层图案。 预备的第二层图案具有基本上低于或基本上等于隔离层的上表面的上表面。 在初步第二层和隔离层上形成第三层。 在第三层上形成第四层。 部分蚀刻第四层，第三层，初步第二层图案和第一层，以在基板上形成栅极结构。 源极/漏极区域形成在与栅极结构相邻的衬底的部分处。

    Methods of Manufacturing Semiconductor Memory Devices with Unit Cells Having Charge Trapping Layers
    2.
    发明申请
    Methods of Manufacturing Semiconductor Memory Devices with Unit Cells Having Charge Trapping Layers 失效
    制造具有电荷陷阱层的单元电池的半导体存储器件的方法

    公开(公告)号：US20070264793A1

    公开(公告)日：2007-11-15

    申请号：US11746761

    申请日：2007-05-10

    申请人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Woo-Gwam Shim ,  Jong-Won Lee

    发明人： Jung-Min Oh ,  Jeong-Nam Han ,  Chang-Ki Hong ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Woo-Gwam Shim ,  Jong-Won Lee

    IPC分类号： H01L21/76

    CPC分类号： H01L27/115 ,  H01L21/76229 ,  H01L27/11568

    摘要： In a method of manufacturing a semiconductor device such as a SONOS type semiconductor device, a trench is formed on a substrate. An isolation layer protruding from the substrate is formed to fill the trench. After a first layer is formed on the substrate, a preliminary second layer pattern is formed on the first layer. The preliminary second layer pattern has an upper face substantially lower than or substantially equal to an upper face of the isolation layer. A third layer is formed on the preliminary second layer and the isolation layer. A fourth layer is formed on the third layer. The fourth layer, the third layer, the preliminary second layer pattern and the first layer are partially etched to form a gate structure on the substrate. Source/drain regions are formed at portions of the substrate adjacent to the gate structure.

    摘要翻译： 在制造诸如SONOS型半导体器件的半导体器件的方法中，在衬底上形成沟槽。 形成从衬底突出的隔离层以填充沟槽。 在基板上形成第一层之后，在第一层上形成预备的第二层图案。 预备的第二层图案具有基本上低于或基本上等于隔离层的上表面的上表面。 在初步第二层和隔离层上形成第三层。 在第三层上形成第四层。 部分蚀刻第四层，第三层，初步第二层图案和第一层，以在基板上形成栅极结构。 源极/漏极区域形成在与栅极结构相邻的衬底的部分处。

    METHODS OF FORMING A THIN FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME
    3.
    发明申请
    METHODS OF FORMING A THIN FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME 失效
    形成薄膜层的方法和制造包括其的半导体器件的方法

    公开(公告)号：US20100015729A1

    公开(公告)日：2010-01-21

    申请号：US12503440

    申请日：2009-07-15

    申请人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

    发明人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

    IPC分类号： H01L21/28

    CPC分类号： H01L27/11507 ,  H01L21/3105 ,  H01L21/31053 ,  H01L28/55

    摘要： In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.

    摘要翻译： 在形成薄铁电体层的方法和制造半导体器件的方法中，通过沉积包括铅，锆和钛的金属氧化物，在衬底上形成初步铁电层。 使用包括丙烯酸聚合物，磨料颗粒和水的浆料组合物对预制铁电层的表面进行抛光，以在基材上形成薄铁电层。 浆料组合物可以降低预备铁电体层的抛光速率，从而可以抑制初级铁电层的体积部分的去除，并且可以提高预铁电层的表面粗糙度。

    Methods of fabricating a semiconductor device
    4.
    发明授权
    Methods of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08084344B2

    公开(公告)日：2011-12-27

    申请号：US12292195

    申请日：2008-11-13

    申请人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/6653

    摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.

    摘要翻译： 提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如 层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

    Polishing pad conditioner and chemical mechanical polishing apparatus having the same
    5.
    发明申请
    Polishing pad conditioner and chemical mechanical polishing apparatus having the same 有权
    抛光垫调节剂及其化学机械抛光装置

    公开(公告)号：US20050113009A1

    公开(公告)日：2005-05-26

    申请号：US10985206

    申请日：2004-11-10

    申请人： Jong-Won Lee ,  Joon-Sang Park ,  Chang-Ki Hong

    发明人： Jong-Won Lee ,  Joon-Sang Park ,  Chang-Ki Hong

    IPC分类号： B24B53/007 ,  B24B53/02 ,  B24B7/00

    CPC分类号： B24B53/017 ,  B24B53/02

    摘要： Chemical mechanical apparatuses including a polishing pad conditioning unit for improving a conditioning rate and wear uniformity of a polishing pad are provided. In one aspect, a chemical mechanical polishing apparatus includes a polishing pad conditioner including conditioning disks disposed in a radial direction of a planarizing surface of a circular polishing pad and contacted with the planarizing surface of the circular polishing pad during rotation of the circular polishing pad. The conditioning disks are connected to first drive units supported by an arm disposed over the circular polishing pad and extended in a radial direction of a planarizing surface of the circular polishing pad. The arm is connected to second drive units. The second drive units move the arm horizontally and reciprocally in the radial direction of the planarizing surface of the circular polishing pad. Thus, a conditioning rate and wear uniformity of the polishing pad may be improved.

    摘要翻译： 提供了包括用于改善抛光垫的调理率和磨损均匀性的抛光垫调节单元的化学机械设备。 在一个方面，一种化学机械抛光装置包括抛光垫调节器，其包括在圆形抛光垫的平坦化表面的径向方向上设置的调节盘，并且在圆形抛光垫的旋转期间与圆形抛光垫的平坦化表面接触。 调节盘连接到由设置在圆形抛光垫上的臂支撑的第一驱动单元，并且在圆形抛光垫的平坦化表面的径向方向上延伸。 臂连接到第二个驱动单元。 第二驱动单元在圆形抛光垫的平坦化表面的径向水平和往复地移动臂。 因此，可以提高抛光垫的调理率和磨损均匀性。

    Methods of fabricating a semiconductor device
    6.
    发明申请
    Methods of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20090155991A1

    公开(公告)日：2009-06-18

    申请号：US12292195

    申请日：2008-11-13

    申请人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    发明人： Jong-Won Lee ,  Sang-Yeob Han ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Jae-Dong Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/6653

    摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.

    摘要翻译： 提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如 层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

    Chemical mechanical polishing apparatus
    9.
    发明授权
    Chemical mechanical polishing apparatus 有权
    化学机械抛光装置

    公开(公告)号：US06887130B2

    公开(公告)日：2005-05-03

    申请号：US10795370

    申请日：2004-03-08

    申请人： Jong-Won Lee ,  Chang-Ki Hong ,  Ho-Young Kim

    发明人： Jong-Won Lee ,  Chang-Ki Hong ,  Ho-Young Kim

    IPC分类号： H01L21/304 ,  B24B37/26 ,  B24B41/04 ,  B24B49/00

    CPC分类号： B24B37/26 ,  B24B41/04

    摘要： A chemical mechanical polishing (CMP) apparatus includes a plate that holds a substrate, a pad assembly unit comprising a pad support device, a positioning device, and a rotation device operatively connected to the pad assembly unit. The pad support device comprises a plurality of support plates to which pad pieces of a polishing pad can be attached. The positioning device can move at least one of the plurality of support plates in a direction along a surface of the semiconductor substrate to be polished. Further, the CMP apparatus can control the polishing amount along any portion of a surface of a wafer to be polished.

    摘要翻译： 化学机械抛光（CMP）装置包括保持基板的板，包括垫支撑装置的垫组件单元，定位装置和可操作地连接到垫组件单元的旋转装置。 垫支撑装置包括多个支撑板，抛光垫的垫片可附接到支撑板上。 定位装置可以沿着要被抛光的半导体衬底的表面的方向移动多个支撑板中的至少一个。 此外，CMP装置可以控制沿抛光晶片的表面的任何部分的抛光量。

    Methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device including the same
    10.
    发明授权
    Methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device including the same 失效
    形成薄铁电体层的方法和制造其的半导体器件的制造方法

    公开(公告)号：US08124526B2

    公开(公告)日：2012-02-28

    申请号：US12503440

    申请日：2009-07-15

    申请人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

    发明人： Suk-Hun Choi ,  Jong-Won Lee ,  Chang-Ki Hong ,  Bo-Un Yoon

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/11507 ,  H01L21/3105 ,  H01L21/31053 ,  H01L28/55

    摘要： In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.

    摘要翻译： 在形成薄铁电体层的方法和制造半导体器件的方法中，通过沉积包括铅，锆和钛的金属氧化物，在衬底上形成初步铁电层。 使用包括丙烯酸聚合物，磨料颗粒和水的浆料组合物对预制铁电层的表面进行抛光，以在基材上形成薄铁电层。 浆料组合物可以降低预备铁电体层的抛光速率，从而可以抑制初级铁电层的体积部分的去除，并且可以提高预铁电层的表面粗糙度。