Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure including a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.