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    Diffuser plate, backlight and display having the same
    2.
    发明授权
    Diffuser plate, backlight and display having the same 有权
    扩散板，背光源和显示屏具有相同的功能

    公开(公告)号：US07864266B2

    公开(公告)日：2011-01-04

    申请号：US12289636

    申请日：2008-10-31

    申请人： Kyung Joon Lee ,  Seung Man Choi ,  Man Suk Kim

    发明人： Kyung Joon Lee ,  Seung Man Choi ,  Man Suk Kim

    IPC分类号： G02F1/1335 ,  F21V11/00

    CPC分类号： G02F1/133611 ,  G02F1/133604 ,  G02F1/133606 ,  G02F2001/133607

    摘要： A diffuser plate includes a first optical sheet having a rear surface configured to receive light from a light source and having a front surface configured to provide light to a second optical sheet, the first optical sheet having a refractive part that includes a plurality of optical members at a surface of the first optical sheet, and a second optical sheet disposed in front of the first optical sheet, the second optical sheet including a rear surface configured to receive light from the first optical sheet, a front surface configured to emit light, and light-scattering beads within the first optical sheet.

    摘要翻译： 扩散板包括第一光学片，其具有被配置为接收来自光源的光并且具有被配置为向第二光学片提供光的前表面的后表面，所述第一光学片具有折射部分，所述折射部分包括多个光学部件 在第一光学片的表面和设置在第一光学片的前方的第二光学片，第二光学片包括被配置为接收来自第一光学片的光的后表面，被配置为发光的前表面，以及 第一光学片内的光散射珠。

    Diffuser plate, backlight and display have the same
    4.
    发明申请
    Diffuser plate, backlight and display have the same 审中-公开
    扩散板，背光源和显示屏都具有相同的功能

    公开(公告)号：US20090128914A1

    公开(公告)日：2009-05-21

    申请号：US12289638

    申请日：2008-10-31

    申请人： Kyung Joon Lee ,  Illia Borysov ,  Seung Man Choi ,  Man Suk Kim ,  Chul Goo Chi ,  Jae Han Kim

    发明人： Kyung Joon Lee ,  Illia Borysov ,  Seung Man Choi ,  Man Suk Kim ,  Chul Goo Chi ,  Jae Han Kim

    IPC分类号： G02B23/00 ,  G02F1/1335

    CPC分类号： G02B5/0278 ,  G02B5/0215 ,  G02B5/0231 ,  G02B5/0284

    摘要： A diffuser plate includes a first optical sheet having a rear surface configured to receive light from a light source and having a front surface configured to provide light to a second optical sheet, the first optical sheet having a predetermined pattern formed by a plurality of transmissive regions and a plurality of reflective regions, and a second optical sheet disposed in front of the first optical sheet, the second optical sheet including a rear surface configured to receive light from the first optical sheet, a front surface configured to emit light, and lenticular lenses on the front surface of the second optical sheet.

    摘要翻译： 扩散板包括第一光学片，其具有被配置为从光源接收光并且具有被配置为向第二光学片提供光的正面的后表面，所述第一光学片具有由多个透射区域形成的预定图案 和多个反射区域，以及设置在第一光学片前方的第二光学片，第二光学片包括被配置为接收来自第一光学片的光的后表面，被配置为发光的前表面和双凸透镜 在第二光学片的前表面上。

    Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics
    6.
    发明授权
    Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics 有权
    使用具有不同孔隙率特性的多个平坦化层在半导体衬底上形成双镶嵌互连结构的方法

    公开(公告)号：US07365025B2

    公开(公告)日：2008-04-29

    申请号：US11348428

    申请日：2006-02-06

    申请人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Oo Kim

    发明人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Oo Kim

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76808 ,  H01L21/31144

    摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole.

    摘要翻译： 形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。 图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。 在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。 至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。 填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。 选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。 电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。

    Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby
    7.
    发明授权
    Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby 有权
    通过选择性地形成扩散阻挡层制造半导体器件的方法和由此制造半导体器件

    公开(公告)号：US07335590B2

    公开(公告)日：2008-02-26

    申请号：US11033189

    申请日：2005-01-11

    申请人： Bong-Seok Suh ,  Ki-Chul Park ,  Seung-Man Choi ,  Il-Ryong Kim

    发明人： Bong-Seok Suh ,  Ki-Chul Park ,  Seung-Man Choi ,  Il-Ryong Kim

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76844 ,  H01L21/2855

    摘要： In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substrate. The insulating layer is patterned, thereby forming an opening for exposing at least a portion of the conductive pattern. Then, a diffusion barrier layer is formed on the semiconductor substrate having the opening, using a selective deposition technique. The diffusion barrier layer is formed to a thickness that is less on the exposed conductive pattern than the thickness of the diffusion barrier layer on the insulating layer exposed inside the opening. Then, the diffusion barrier layer is etched, thereby forming a recessed diffusion barrier layer. In this manner, metal atoms are prevented from being diffused from a metal plug filling the opening or a metal interconnect to the insulating layer.

    摘要翻译： 在通过选择性地形成扩散阻挡层制造半导体器件的方法及其制造的半导体器件中，在半导体衬底上形成覆盖导电图案的导电图案和绝缘层。 对绝缘层进行图案化，从而形成用于暴露导电图案的至少一部分的开口。 然后，使用选择性沉积技术在具有开口的半导体衬底上形成扩散阻挡层。 扩散阻挡层形成为暴露在导电图案上的厚度小于暴露在开口内部的绝缘层上的扩散阻挡层的厚度。 然后，对扩散阻挡层进行蚀刻，从而形成凹陷扩散阻挡层。 以这种方式，防止金属原子从填充开口的金属插塞或与绝缘层的金属互连扩散。

    Methods for forming damascene wiring structures having line and plug conductors formed from different materials
    8.
    发明申请
    Methods for forming damascene wiring structures having line and plug conductors formed from different materials 有权
    用于形成具有由不同材料形成的线和插头导体的镶嵌线结构的方法

    公开(公告)号：US20070155165A1

    公开(公告)日：2007-07-05

    申请号：US11323328

    申请日：2005-12-30

    申请人： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

    发明人： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76877 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure comprising a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.

    摘要翻译： 提供了用于形成使用不同导体材料填充通孔和线沟槽的双镶嵌互连结构的方法。 例如，用于形成互连结构的方法包括在半导体衬底上沉积介电材料并蚀刻电介质材料以形成包括通孔和沟槽的双镶嵌凹部结构。 然后共形沉积第一导电材料层以用第一导电材料填充通孔，并且蚀刻第一导电材料层以从沟槽移除第一导电材料，并且在沟槽下方的通孔的上部区域 。 然后沉积第二导电材料层，以用第二导电材料填充通孔的沟槽和上部区域。

    Semiconductor device and method of manufacturing the same
    9.
    发明申请
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US20060009065A1

    公开(公告)日：2006-01-12

    申请号：US11174864

    申请日：2005-07-05

    申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

    发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

    IPC分类号： H01R4/24

    CPC分类号： H01L23/5223 ,  H01L21/76808 ,  H01L21/76877 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

    摘要翻译： 在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。 沿着第一开口的内轮廓形成下电极。 第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有阶梯部分的第一开口。 在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。 在电介质层上形成上电极。 因此，抑制了下电极和上电极之间的漏电流。

    Semiconductor device having multi-layer copper line and method of forming same
    10.
    发明授权
    Semiconductor device having multi-layer copper line and method of forming same 有权
    具有多层铜线的半导体器件及其形成方法

    公开(公告)号：US06884710B2

    公开(公告)日：2005-04-26

    申请号：US10338908

    申请日：2003-01-09

    申请人： Ki-Chul Park ,  Seung-Man Choi

    发明人： Ki-Chul Park ,  Seung-Man Choi

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

    CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76847 ,  H01L21/76868 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a lower copper line formed on a substrate, an interlayer insulating layer formed on the lower copper line, and an upper copper line formed on the interlayer insulating layer. A copper via contact extends through the interlayer insulating layer for electrically connecting the lower copper line and the upper copper line. A concave recess is formed within the lower copper line and is vertically aligned and arranged below the copper via contact. A patterned barrier layer is formed at a bottom portion of the concave recess, such that the lower copper line and the copper via contact are directly electrically connected at an interface along sides of the concave recess, without an intervening barrier layer.

    摘要翻译： 半导体器件包括形成在衬底上的下铜线，形成在下铜线上的层间绝缘层和形成在层间绝缘层上的上铜线。 铜通孔接触件延伸穿过层间绝缘层，用于电连接下铜线和上铜线。 在下铜线内部形成一个凹槽，并且垂直对齐并布置在铜通孔接触处的下方。 图案化的阻挡层形成在凹形凹部的底部，使得下铜线和铜通路接触部在沿着凹形凹部的侧面的界面处直接电连接，而没有中间的阻挡层。