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    Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities
    1.
    发明申请
    Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities 有权
    使用具有高应力特性的绝缘层的CMOS集成电路的形成方法来改善NMOS和PMOS晶体管载体的迁移率

    公开(公告)号：US20090124093A1

    公开(公告)日：2009-05-14

    申请号：US12353519

    申请日：2009-01-14

    Applicant: Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

    Inventor： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

    IPC: H01L21/469

    CPC classification number: H01L21/823807 ,  H01L29/7843

    Abstract: A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

    Abstract translation: CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。 提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。 特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

    Methods for forming damascene wiring structures having line and plug conductors formed from different materials
    2.
    发明授权
    Methods for forming damascene wiring structures having line and plug conductors formed from different materials 有权
    用于形成具有由不同材料形成的线和插头导体的镶嵌线结构的方法

    公开(公告)号：US07514354B2

    公开(公告)日：2009-04-07

    申请号：US11323328

    申请日：2005-12-30

    Applicant: Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

    Inventor： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

    IPC: H01L21/4763

    CPC classification number: H01L21/76877 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure including a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.

    Abstract translation: 提供了用于形成使用不同导体材料填充通孔和线沟槽的双镶嵌互连结构的方法。 例如，形成互连结构的方法包括在半导体衬底上沉积介电材料并蚀刻电介质材料以形成包括通孔和沟槽的双镶嵌凹部结构。 然后共形沉积第一导电材料层以用第一导电材料填充通孔，并且蚀刻第一导电材料层以从沟槽移除第一导电材料，并且在沟槽下方的通孔的上部区域 。 然后沉积第二导电材料层，以用第二导电材料填充通孔的沟槽和上部区域。

    Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method
    3.
    发明授权
    Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method 有权
    形成半导体器件的金属互连的方法以及通过这种方法形成的金属互连

    公开(公告)号：US07446033B2

    公开(公告)日：2008-11-04

    申请号：US11336905

    申请日：2006-01-23

    Applicant: Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

    Inventor： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

    IPC: H01L21/4763 ,  H01L21/44

    CPC classification number: H01L21/76877 ,  H01L21/7684 ,  H01L21/76883 ,  Y10T428/24207

    Abstract: A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.

    Abstract translation: 使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。 首先，在层间电介质层的开口中依次形成阻挡层和金属层。 在金属层上进行CMP工艺以形成残留在开口内的金属互连。 然后，用等离子体处理金属互连。 等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。 此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。 然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。 最后，形成封盖绝缘层。 通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。

    Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization
    4.
    发明授权
    Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization 有权
    用于形成用于铜基金属化的氢填充沟槽衬垫的物理气相沉积方法

    公开(公告)号：US07387962B2

    公开(公告)日：2008-06-17

    申请号：US11251947

    申请日：2005-10-17

    Applicant: Kyoung-Woo Lee ,  Seung-Man Choi

    Inventor： Kyoung-Woo Lee ,  Seung-Man Choi

    IPC: H01L21/44

    CPC classification number: H01L21/2855 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76873

    Abstract: Copper-based metallization is formed in a trench on an integrated circuit substrate by forming a liner of refractory metal in the trench using physical vapor deposition, forming a copper plating seed layer on the liner using physical vapor deposition and then plating copper on the copper plating seed layer. Prior to plating copper on the copper plating seed layer, the liner and/or copper plating seed layer is stuffed with hydrogen, for example by exposing the liner and/or copper plating seed layer to a hydrogen-containing plasma during and/or after formation of the liner and/or copper plating seed layer. Related structures also are disclosed.

    Abstract translation: 通过使用物理气相沉积在沟槽中形成难熔金属的衬垫，在集成电路衬底的沟槽中形成铜基金属化，使用物理气相沉积在衬套上形成铜电镀种子层，然后在铜电镀上镀铜 种子层。 在镀铜种子层上镀铜之前，衬里和/或铜电镀种子层被填充氢，例如通过在形成期间和/或之后将衬里和/或铜电镀种子层暴露于含氢等离子体 的衬里和/或铜电镀种子层。 还公开了相关结构。

    Metal-insulator-metal (MIM) capacitor and method of fabricating the same
    6.
    发明授权
    Metal-insulator-metal (MIM) capacitor and method of fabricating the same 有权
    金属绝缘体金属（MIM）电容器及其制造方法

    公开(公告)号：US07332764B2

    公开(公告)日：2008-02-19

    申请号：US11080567

    申请日：2005-03-16

    Applicant: Seung-Man Choi ,  Ki-Chul Park ,  Bong-Seok Suh ,  Il-Ryong Kim

    Inventor： Seung-Man Choi ,  Ki-Chul Park ,  Bong-Seok Suh ,  Il-Ryong Kim

    IPC: H01L29/76

    CPC classification number: H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and the interlayer insulating layer, a via hole exposing the lower metal interconnection, an upper metal interconnection groove crossing over the via hole, at least one capacitor trench region exposing the lower metal electrode, an upper metal interconnection filling the upper metal interconnection groove, the upper metal interconnection being electrically connected to the lower metal interconnection through the via hole, a dielectric layer covering inner surfaces of the at least one capacitor trench region, and an upper metal electrode surrounded by the dielectric layer to fill the at least one capacitor trench region.

    Abstract translation: 在MIM电容器及其制造方法中，MIM电容器包括在半导体衬底上的层间绝缘层，层间绝缘层中的下部金属互连和下部金属电极，覆盖下部金属互连的金属间介电层， 下金属电极和层间绝缘层，暴露下金属互连的通孔，与通孔相交的上金属互连槽，暴露下金属电极的至少一个电容器沟槽区，填充上金属互连的上金属互连 金属互连槽，所述上金属互连通过所述通孔电连接到所述下金属互连，覆盖所述至少一个电容器沟槽区的内表面的电介质层和被所述电介质层包围的上金属电极以填充 至少一个电容器沟槽区域。

    Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization, and resultant structures
    7.
    发明申请
    Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization, and resultant structures 有权
    用于形成用于铜基金属化的氢填充沟槽衬垫的物理气相沉积方法，以及所得结构

    公开(公告)号：US20070087567A1

    公开(公告)日：2007-04-19

    申请号：US11251947

    申请日：2005-10-17

    Applicant: Kyoung-Woo Lee ,  Seung-Man Choi

    Inventor： Kyoung-Woo Lee ,  Seung-Man Choi

    IPC: H01L21/44 ,  H01L21/4763

    CPC classification number: H01L21/2855 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76873

    Abstract: Copper-based metallization is formed in a trench on an integrated circuit substrate by forming a liner of refractory metal in the trench using physical vapor deposition, forming a copper plating seed layer on the liner using physical vapor deposition and then plating copper on the copper plating seed layer. Prior to plating copper on the copper plating seed layer, the liner and/or copper plating seed layer is stuffed with hydrogen, for example by exposing the liner and/or copper plating seed layer to a hydrogen-containing plasma during and/or after formation of the liner and/or copper plating seed layer. Related structures also are disclosed.

    Abstract translation: 通过使用物理气相沉积在沟槽中形成难熔金属的衬垫，在集成电路衬底的沟槽中形成铜基金属化，使用物理气相沉积在衬套上形成铜电镀种子层，然后在铜电镀上镀铜 种子层。 在镀铜种子层上镀铜之前，衬里和/或铜电镀种子层被填充氢，例如通过在形成期间和/或之后将衬里和/或铜电镀种子层暴露于含氢等离子体 的衬里和/或铜电镀种子层。 还公开了相关结构。

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