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    Methods for forming damascene wiring structures having line and plug conductors formed from different materials
    1.
    发明授权
    Methods for forming damascene wiring structures having line and plug conductors formed from different materials 有权
    用于形成具有由不同材料形成的线和插头导体的镶嵌线结构的方法

    公开(公告)号：US07514354B2

    公开(公告)日：2009-04-07

    申请号：US11323328

    申请日：2005-12-30

    申请人： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

    发明人： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76877 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure including a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.

    摘要翻译： 提供了用于形成使用不同导体材料填充通孔和线沟槽的双镶嵌互连结构的方法。 例如，形成互连结构的方法包括在半导体衬底上沉积介电材料并蚀刻电介质材料以形成包括通孔和沟槽的双镶嵌凹部结构。 然后共形沉积第一导电材料层以用第一导电材料填充通孔，并且蚀刻第一导电材料层以从沟槽移除第一导电材料，并且在沟槽下方的通孔的上部区域 。 然后沉积第二导电材料层，以用第二导电材料填充通孔的沟槽和上部区域。

    Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics
    2.
    发明申请
    Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics 有权
    使用具有不同孔隙率特性的多个平坦化层在半导体衬底上形成双镶嵌互连结构的方法

    公开(公告)号：US20070184649A1

    公开(公告)日：2007-08-09

    申请号：US11348428

    申请日：2006-02-06

    申请人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Kim

    发明人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Kim

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/31144

    摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole. The first electrically insulating material, which has a relatively high degree of porosity, is then removed from the at least one via hole. This removal step may be performed using a relatively mild ashing process because of the high porosity of the first electrically insulating material.

    摘要翻译： 形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。 图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。 在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。 至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。 填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。 选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。 电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。 然后从该至少一个通孔去除具有较高孔隙率的第一电绝缘材料。 由于第一电绝缘材料的高孔隙率，该去除步骤可以使用相对温和的灰化过程进行。

    Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics
    3.
    发明授权
    Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics 有权
    使用具有不同孔隙率特性的多个平坦化层在半导体衬底上形成双镶嵌互连结构的方法

    公开(公告)号：US07365025B2

    公开(公告)日：2008-04-29

    申请号：US11348428

    申请日：2006-02-06

    申请人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Oo Kim

    发明人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Oo Kim

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76808 ,  H01L21/31144

    摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole.

    摘要翻译： 形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。 图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。 在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。 至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。 填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。 选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。 电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。

    Methods for forming damascene wiring structures having line and plug conductors formed from different materials
    4.
    发明申请
    Methods for forming damascene wiring structures having line and plug conductors formed from different materials 有权
    用于形成具有由不同材料形成的线和插头导体的镶嵌线结构的方法

    公开(公告)号：US20070155165A1

    公开(公告)日：2007-07-05

    申请号：US11323328

    申请日：2005-12-30

    申请人： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

    发明人： Ki-Chul Park ,  Ja-Hum Ku ,  Seung-Man Choi

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76877 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure comprising a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.

    摘要翻译： 提供了用于形成使用不同导体材料填充通孔和线沟槽的双镶嵌互连结构的方法。 例如，用于形成互连结构的方法包括在半导体衬底上沉积介电材料并蚀刻电介质材料以形成包括通孔和沟槽的双镶嵌凹部结构。 然后共形沉积第一导电材料层以用第一导电材料填充通孔，并且蚀刻第一导电材料层以从沟槽移除第一导电材料，并且在沟槽下方的通孔的上部区域 。 然后沉积第二导电材料层，以用第二导电材料填充通孔的沟槽和上部区域。

    Metal-insulator-metal (MIM) capacitor and method of fabricating the same
    9.
    发明授权
    Metal-insulator-metal (MIM) capacitor and method of fabricating the same 有权
    金属绝缘体金属（MIM）电容器及其制造方法

    公开(公告)号：US07332764B2

    公开(公告)日：2008-02-19

    申请号：US11080567

    申请日：2005-03-16

    申请人： Seung-Man Choi ,  Ki-Chul Park ,  Bong-Seok Suh ,  Il-Ryong Kim

    发明人： Seung-Man Choi ,  Ki-Chul Park ,  Bong-Seok Suh ,  Il-Ryong Kim

    IPC分类号： H01L29/76

    CPC分类号： H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and the interlayer insulating layer, a via hole exposing the lower metal interconnection, an upper metal interconnection groove crossing over the via hole, at least one capacitor trench region exposing the lower metal electrode, an upper metal interconnection filling the upper metal interconnection groove, the upper metal interconnection being electrically connected to the lower metal interconnection through the via hole, a dielectric layer covering inner surfaces of the at least one capacitor trench region, and an upper metal electrode surrounded by the dielectric layer to fill the at least one capacitor trench region.

    摘要翻译： 在MIM电容器及其制造方法中，MIM电容器包括在半导体衬底上的层间绝缘层，层间绝缘层中的下部金属互连和下部金属电极，覆盖下部金属互连的金属间介电层， 下金属电极和层间绝缘层，暴露下金属互连的通孔，与通孔相交的上金属互连槽，暴露下金属电极的至少一个电容器沟槽区，填充上金属互连的上金属互连 金属互连槽，所述上金属互连通过所述通孔电连接到所述下金属互连，覆盖所述至少一个电容器沟槽区的内表面的电介质层和被所述电介质层包围的上金属电极以填充 至少一个电容器沟槽区域。

    Metal-insulator-metal (MIM) capacitor and method of fabricating the same
    10.
    发明申请
    Metal-insulator-metal (MIM) capacitor and method of fabricating the same 有权
    金属绝缘体金属（MIM）电容器及其制造方法

    公开(公告)号：US20050275005A1

    公开(公告)日：2005-12-15

    申请号：US11080567

    申请日：2005-03-16

    申请人： Seung-Man Choi ,  Ki-Chul Park ,  Bong-Seok Suh ,  Il-Ryong Kim

    发明人： Seung-Man Choi ,  Ki-Chul Park ,  Bong-Seok Suh ,  Il-Ryong Kim

    IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  H01L29/76

    CPC分类号： H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and the interlayer insulating layer, a via hole exposing the lower metal interconnection, an upper metal interconnection groove crossing over the via hole, at least one capacitor trench region exposing the lower metal electrode, an upper metal interconnection filling the upper metal interconnection groove, the upper metal interconnection being electrically connected to the lower metal interconnection through the via hole, a dielectric layer covering inner surfaces of the at least one capacitor trench region, and an upper metal electrode surrounded by the dielectric layer to fill the at least one capacitor trench region.

    摘要翻译： 在MIM电容器及其制造方法中，MIM电容器包括在半导体衬底上的层间绝缘层，层间绝缘层中的下部金属互连和下部金属电极，覆盖下部金属互连的金属间介电层， 下金属电极和层间绝缘层，暴露下金属互连的通孔，与通孔相交的上金属互连槽，暴露下金属电极的至少一个电容器沟槽区，填充上金属互连的上金属互连 金属互连槽，所述上金属互连通过所述通孔电连接到所述下金属互连，覆盖所述至少一个电容器沟槽区的内表面的电介质层和被所述电介质层包围的上金属电极以填充 至少一个电容器沟槽区域。