发明授权
US07521951B1 Non-invasive, low pin count test circuits and methods utilizing emulated stress conditions
有权
非侵入性，低引脚数测试电路和利用模拟应力条件的方法
- 专利标题： Non-invasive, low pin count test circuits and methods utilizing emulated stress conditions
- 专利标题（中）： 非侵入性，低引脚数测试电路和利用模拟应力条件的方法
-
申请号： US11402508申请日： 2006-04-12
-
公开(公告)号： US07521951B1公开(公告)日： 2009-04-21
- 发明人: Murari Kejariwal , John Laurence Melanson , Ammisetti V. Prasad , Sherry Xiaohong Wu
- 申请人： Murari Kejariwal , John Laurence Melanson , Ammisetti V. Prasad , Sherry Xiaohong Wu
- 申请人地址： US TX Austin
- 专利权人： Cirrus Logic, Inc.
- 当前专利权人： Cirrus Logic, Inc.
- 当前专利权人地址： US TX Austin
- 代理机构： Thompson & Knight LLP
- 代理商 James J. Murphy
- 主分类号： G01R31/02
- IPC分类号： G01R31/02
摘要：
A method of testing an internal block of an integrated circuit includes initiating a test mode and verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. A test signal is selectively output from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
信息查询
