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1.发明授权Non-invasive, low pin count test circuits and methods utilizing emulated stress conditions 有权非侵入性，低引脚数测试电路和利用模拟应力条件的方法公开(公告)号：US07521951B1
公开(公告)日：2009-04-21
申请号：US11402508
申请日：2006-04-12
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： A method of testing an internal block of an integrated circuit includes initiating a test mode and verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. A test signal is selectively output from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
摘要翻译： 一种测试集成电路的内部块的方法包括在与其他操作模式中的条件相比较下，在测试模式中在更严格的条件下启动测试模式并验证集成电路的操作，使得集成电路 在另一个操作模式下保证。 在指示内部块的操作的测试模式中，选择性地从所选择的引脚输出测试信号，其中当集成电路处于另一操作模式时，所选择的引脚用于交换另一个信号。
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2.发明授权Non-invasive, low pin count test circuits and methods utilizing emulated stress conditions 有权非侵入性，低引脚数测试电路和利用模拟应力条件的方法公开(公告)号：US07808263B2
公开(公告)日：2010-10-05
申请号：US12381774
申请日：2009-03-17
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
摘要翻译： 一种集成电路，包括至少一个内部操作块，其包括用于启动测试模式的测试控制电路和用于在测试模式中在更严格的条件下验证集成电路的操作的测试电路，与其他操作模式中的条件相比 使得在另一操作模式下确保集成电路的正确操作。 引脚控制电路在指示内部块的操作的测试模式中选择性地输出来自所选引脚的测试信号，其中当集成电路处于另一操作模式时，所选择的引脚用于交换另一信号。
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3.发明申请Non-invasiv, low pin count test circuits and methods utilizing emulated stress conditions 有权非侵入式，低引脚数测试电路和利用模拟应力条件的方法公开(公告)号：US20090179660A1
公开(公告)日：2009-07-16
申请号：US12381774
申请日：2009-03-17
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
摘要翻译： 一种集成电路，包括至少一个内部操作块，其包括用于启动测试模式的测试控制电路和用于在测试模式中在更严格的条件下验证集成电路的操作的测试电路，与其他操作模式中的条件相比 使得在另一操作模式下确保集成电路的正确操作。 引脚控制电路在指示内部块的操作的测试模式中选择性地输出来自所选引脚的测试信号，其中当集成电路处于另一操作模式时，所选择的引脚用于交换另一信号。
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4.发明授权公开(公告)号：US06515540B1
公开(公告)日：2003-02-04
申请号：US10013559
申请日：2001-12-10
IPC分类号： H03F102
摘要： An amplifier is disclosed including multiple integrator stages. The amplifier includes a low-frequency path from a signal input to a signal output and relatively higher-frequency bypass paths around the first integrator stage. The paths converge at a summing node. To prevent instability when the integrators are saturated by large signals, the circuit includes a saturation detector which disables the relatively low-frequency paths during such saturation conditions.
摘要翻译： 公开了包括多个积分器级的放大器。 放大器包括从信号输入到信号输出的低频路径和围绕第一积分器级的相对较高频率的旁路路径。 路径收敛在求和节点处。 为了防止当积分器被大信号饱和时的不稳定性，该电路包括饱和检测器，其在这种饱和状态期间禁用相对低频路径。
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公开(公告)号：US07639002B1
公开(公告)日：2009-12-29
申请号：US11410362
申请日：2006-04-25
IPC分类号： G01R31/28
CPC分类号： G01R31/31707
摘要： A method of testing an integrated circuit including a plurality of test nodes includes initiating a test mode and, during a first time interval of the test mode, stepping a level of a supply current of the integrated circuit to a calibration level. Parameters are observed at the plurality of test nodes to detect errors during a second time interval of the test mode and the level of the supply current selectively stepped in response to a number of errors detected. The level of the supply current is decoded to identify the detected errors.
摘要翻译： 一种测试包括多个测试节点的集成电路的方法包括启动测试模式，并且在测试模式的第一时间间隔期间，使集成电路的电源电平的级别达到校准水平。 在多个测试节点处观察参数以在测试模式的第二时间间隔期间检测错误，并且响应于检测到的错误的数量选择性地步进电源电平。 电源电流的电平被解码以识别检测到的错误。
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公开(公告)号：US06937046B1
公开(公告)日：2005-08-30
申请号：US10027187
申请日：2001-12-20
CPC分类号： G01R31/2884
摘要： A method of testing an integrated circuit including the steps of observing a selected parameter at a selected test mode to detect an error. The current to the integrated circuit is stepped from a reference level by selected amount.
摘要翻译： 一种测试集成电路的方法，包括在所选择的测试模式下观察所选择的参数以检测错误的步骤。 到集成电路的电流从参考电平以选定的量步进。
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公开(公告)号：US06885211B1
公开(公告)日：2005-04-26
申请号：US10117374
申请日：2002-04-05
CPC分类号： G01R31/2837
摘要： A method of testing an integrated circuit includes setting a guardbanded limit for a parameter associated with an embedded node, a deviation from the guardbanded limit under a set of test conditions correlated with a failure of the integrated circuit across a range of operating conditions. A test is performed under the test conditions to detect deviations of the parameter from the guardbanded limit to detect failures of the integrated circuit over the range of operating conditions.
摘要翻译： 一种测试集成电路的方法包括设置与嵌入式节点相关联的参数的保护限值，与在整个操作条件范围内的集成电路的故障相关的一组测试条件下的保护带限制的偏差。 在测试条件下进行测试，以检测参数与防护带限制的偏差，以检测集成电路在工作条件范围内的故障。
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公开(公告)号：US20070217544A1
公开(公告)日：2007-09-20
申请号：US11378009
申请日：2006-03-17
申请人： Murari Kejariwal , John Coupe
发明人： Murari Kejariwal , John Coupe
CPC分类号： H03F3/45188 , H03F3/45475 , H03F2200/331 , H03F2203/45032 , H03F2203/45371 , H03F2203/45396 , H03F2203/45486 , H03F2203/45504 , H03F2203/45631 , H03F2203/45634 , H03F2203/45726 , H03G1/0029 , H03G1/0088 , H03M1/129
摘要： A data acquisition system includes a programmable gain amplifier, an analog-to-digital converter, a filter, and control circuitry. The programmable gain amplifier is operatively connected to receive an analog input signal on its input and generates an amplified signal on its output in accordance with gain control signals. The analog-to-digital converter is operatively connected to receive the amplified signal from the amplifier and generates a digitized signal on its output. The filter is operatively connected to receive the digitized signal from the converter and generates a filtered digital signal on its output. The control circuitry is operatively connected to the amplifier and to the converter and is also responsive to the gain control signals for dynamically adjusting power between the amplifier and converter when the gain control signals are changed.
摘要翻译： 数据采集系统包括可编程增益放大器，模数转换器，滤波器和控制电路。 可编程增益放大器可操作地连接以在其输入上接收模拟输入信号，并根据增益控制信号在其输出上产生放大信号。 模数转换器可操作地连接以从放大器接收放大的信号，并在其输出端产生数字化信号。 滤波器可操作地连接以接收来自转换器的数字化信号，并在其输出端产生滤波后的数字信号。 控制电路可操作地连接到放大器和转换器，并且当增益控制信号改变时也响应于增益控制信号来动态调整放大器和转换器之间的功率。
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9.发明授权公开(公告)号：US07202746B1
公开(公告)日：2007-04-10
申请号：US11011443
申请日：2004-12-14
IPC分类号： H03F3/04
CPC分类号： H03F3/45 , H03F1/08 , H03F3/45937 , H03F3/68 , H03F2203/45512
摘要： A multiple-stage operational amplifier including a gain stage for amplifying an input signal and implementing a dominant pole producing a frequency response having a gain roll-off with frequency and a unity gain frequency. An intermediate stage is coupled to an output of the gain stage and has a high input impedance and a low output impedance. A high gain amplifier configured as a low gain output stage using resistive feedback and coupled to an output of the intermediate stage drives an output of the operational amplifier and implements a dominant pole at a frequency substantially higher than the unity gain frequency implemented by the dominant pole implemented the gain stage.
摘要翻译： 一种多级运算放大器，包括用于放大输入信号的增益级和实现具有频率和单位增益频率的具有增益滚降的频率响应的主导极。 中间级耦合到增益级的输出，并具有高输入阻抗和低输出阻抗。 配置为低增益输出级的高增益放大器，使用电阻反馈并耦合到中间级的输出，驱动运算放大器的输出，并以比由主极实现的单位增益频率显着更高的频率实现主极点 实施增益阶段。
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10.发明申请Circuits and methods for minimizing chopping artifacts at the output of a chopper-stabilized operational amplifier 有权用于最小化斩波稳定运算放大器输出端的斩波伪影的电路和方法公开(公告)号：US20060158244A1
公开(公告)日：2006-07-20
申请号：US11036082
申请日：2005-01-14
IPC分类号： H03F1/02
CPC分类号： H03F3/387 , H03F2200/261
摘要： An operational amplifier including at least one amplifier stage and chopping circuitry for chopping an input signal to the amplifier stage and an output signal from the chopping signal having a frequency randomly varying within the selected frequency band.
摘要翻译： 一种运算放大器，包括至少一个放大器级和用于将输入信号斩波到放大器级的斩波电路以及来自具有在所选频带内随机变化的频率的斩波信号的输出信号。
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