发明授权
US07531442B2 Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing
失效
消除后引线键合芯片中的IMC裂纹:在Cu / Low-K处理期间通过改变介电层/金属膜堆叠层的宏观级应力降低
- 专利标题: Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing
- 专利标题(中): 消除后引线键合芯片中的IMC裂纹:在Cu / Low-K处理期间通过改变介电层/金属膜堆叠层的宏观级应力降低
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申请号: US11290087申请日: 2005-11-30
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公开(公告)号: US07531442B2公开(公告)日: 2009-05-12
- 发明人: Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao , Peter Burke , Ramaswamy Ranganathan , Qwai Low
- 申请人: Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao , Peter Burke , Ramaswamy Ranganathan , Qwai Low
- 申请人地址: US CA Milpitas
- 专利权人: LSI Corporation
- 当前专利权人: LSI Corporation
- 当前专利权人地址: US CA Milpitas
- 代理机构: Trexler, Bushnell, Giangiorgi & Blackstone Ltd.
- 主分类号: H01L21/44
- IPC分类号: H01L21/44
摘要:
Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.
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