Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE)
    1.
    发明授权
    Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE) 有权
    使用自动测试设备(ATE)智能软件的半导体设备的故障分析和测试

    公开(公告)号:US07430700B2

    公开(公告)日:2008-09-30

    申请号:US11670031

    申请日:2007-02-01

    申请人: Roger Yacobucci

    发明人: Roger Yacobucci

    IPC分类号: G06F11/00 G06F17/50 G01R31/28

    CPC分类号: G01R31/318544 G01R31/3193

    摘要: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.

    摘要翻译: 本发明提供了一些改进集成电路器件测试和分析的相关方法。 本发明的第一种方法提供了一种在基于SCAN的测试中暂停的方法。 本发明的第二种方法提供了一种使用已知良好装置的刺激和响应来增加测试流中图案的故障覆盖的方法。 本发明的第三种方法提供了一种在ATE上曲线追踪装置缓冲器的方法。

    Method of generating test patterns to efficiently screen inline resistance delay defects in complex asics
    2.
    发明授权
    Method of generating test patterns to efficiently screen inline resistance delay defects in complex asics 失效
    生成测试模式的方法,以有效地屏蔽复杂的线上电阻延迟缺陷

    公开(公告)号:US07395478B2

    公开(公告)日:2008-07-01

    申请号:US11682914

    申请日:2007-03-07

    申请人: Robert B. Benware

    发明人: Robert B. Benware

    IPC分类号: G01R31/28

    CPC分类号: G06F11/24

    摘要: A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.

    摘要翻译: 一种用于生成基于扫描的转换模式(即,用于转换延迟故障(“TDF”)的ATPG模式生成)的方法,其中当检测到缓慢升高(STR)或降低(STF)转换故障时 该特定故障从故障范围以及其伴随的TDF中消除,其中伴随故障是与检测到的故障相同的节点上的故障,但具有相反的过渡。 换句话说,如果检测到缓慢上升(STR)转换故障,则从故障范围中消除慢升(STR)转换故障以及相应的降低(STF)转换 故障(反之亦然)。 通过去除伴随的故障以及具体检测到的故障,模式生成运行时间以及最终延迟测试模式的总模式计数减少。

    Process window compliant corrections of design layout
    3.
    发明授权
    Process window compliant corrections of design layout 有权
    过程窗口符合设计布局校正

    公开(公告)号:US07313508B2

    公开(公告)日:2007-12-25

    申请号:US10330929

    申请日:2002-12-27

    IPC分类号: G06F17/50

    CPC分类号: G03F1/36

    摘要: The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.

    摘要翻译: 本发明提供了一种执行设计布局的兼容过程窗口校正的方法。 本发明包括一个操作员执行以下步骤:(1)使用提供的原始布局模式在最佳曝光条件下模拟发现检查临界尺寸(DI CD); (2)使用提供的原始布局图案在预定边界曝光条件下模拟DI CD; (3)如果来自步骤(1)的DI CD符合目标DI CD定义,并且步骤(2)的DI CD符合过程窗口规范,则会发生收敛; (4)如果没有实现步骤(3)的任何部分,则修改布局图案并重复步骤(2)至(3),直到来自步骤(2)的DI CD达到规格极限。

    Method to improve the control of source chemicals delivery by a carrier gas
    4.
    发明授权
    Method to improve the control of source chemicals delivery by a carrier gas 失效
    改善载气对源化学品输送控制的方法

    公开(公告)号:US06917430B2

    公开(公告)日:2005-07-12

    申请号:US10172849

    申请日:2002-06-17

    摘要: A method and control system for controlling the delivery of a source chemical by a carrier gas. The carrier gas is delivered to a vessel containing the source chemical, and a flow of source chemical and carrier gas is carried from the vessel along a flow line. A sensor is used to detect light absorption of the flow, and the flow is adjusted based on what is detected. The sensor provides that light is directed transversely through the flow line and that the intensity of the light which passes through the flow line is detected by a detector. The detector forwards an output signal to a signal processing unit which thereafter adjusts the flow based on what was detected. The light may be filtered. The flow line includes at least a portion which provides an optical window for allowing light to pass therethrough.

    摘要翻译: 一种用于控制由载气输送源化学品的方法和控制系统。 载气被输送到含有源化学物质的容器中,并且源化学物质和载气流从容器沿着流动线输送。 传感器用于检测流量的光吸收,并根据检测到的内容调整流量。 传感器提供了光线横穿流线并且通过检测器检测通过流动线的光的强度。 检测器将输出信号转发到信号处理单元,该信号处理单元此后根据检测到的内容调整流量。 灯可能被过滤。 流动线包括至少一部分,其提供用于允许光通过的光学窗口。

    Robust high density substrate design for thermal cycling reliability
    7.
    发明授权
    Robust high density substrate design for thermal cycling reliability 有权
    坚固的高密度基板设计,用于热循环可靠性

    公开(公告)号:US07345245B2

    公开(公告)日:2008-03-18

    申请号:US10681554

    申请日:2003-10-08

    IPC分类号: H05K1/16

    摘要: A semiconductor package for a die with improved thermal cycling reliability. A first layer of the package provides ball pads dispersed throughout. A second layer of the package provides signal traces. A high stress area associated with the corner of the dies is defined. Preferably the high stress area is defined as two ball pitches away from the corner of the die. Signal traces are routed away from the high stress area and in particular signal traces are routed away from the ball pads associated with the high stress to eliminate the cracks in the routed traces.

    摘要翻译: 一种具有改善热循环可靠性的模具的半导体封装。 包装的第一层提供分散在其中的球垫。 封装的第二层提供信号迹线。 定义了与模具角部相关联的高应力区域。 优选地,高应力区域被定义为远离模具角部的两个球距。 信号迹线远离高应力区域,特别是信号迹线远离与高应力相关的球垫,以消除路由迹线中的裂纹。

    Wafer edge structure measurement method
    8.
    发明授权
    Wafer edge structure measurement method 有权
    晶圆边缘结构测量方法

    公开(公告)号:US07312880B2

    公开(公告)日:2007-12-25

    申请号:US10925497

    申请日:2004-08-24

    IPC分类号: G01B11/14

    CPC分类号: G01N21/9503

    摘要: A method of determining the distance from an edge feature to a wafer edge. The wafer is put onto an image acquisition tool, and images are captured and classified. Based on the coordinates of the images and their classifications, the distance between an edge feature and the wafer edge is determined. Reference marks can be etched into the wafer to facilitate the measurement. The measurement technique is objective, and can be used to minimize the edge exclusion ring as well as defects that originate from the edge of the wafer.

    摘要翻译: 确定从边缘特征到晶片边缘的距离的方法。 将晶片放置在图像采集工具上,并对图像进行捕获和分类。 基于图像的坐标及其分类,确定边缘特征与晶片边缘之间的距离。 可以将参考标记蚀刻到晶片中以便于测量。 测量技术是客观的,可用于最小化边缘排除环以及源自晶片边缘的缺陷。

    Method and control system for improving CMP process by detecting and reacting to harmonic oscillation
    9.
    发明授权
    Method and control system for improving CMP process by detecting and reacting to harmonic oscillation 失效
    通过检测和谐波振荡反应来改善CMP工艺的方法和控制系统

    公开(公告)号:US06971944B2

    公开(公告)日:2005-12-06

    申请号:US10779966

    申请日:2004-02-17

    IPC分类号: B24B37/04 B24B49/10 B24B1/00

    CPC分类号: B24B37/005 B24B49/10

    摘要: A method and control system for detecting harmonic oscillation in a chemical mechanical polishing process and reacting thereto, such as by taking steps to at least one of: 1) reduce or eliminate the harmonic oscillation; and 2) counter the noise which is associated with the harmonic oscillation. By reducing or eliminating harmonic oscillation, films with reduced structure strengths including low k dielectric films can be used. By countering the noise, the quality of the work environment is improved.

    摘要翻译: 一种用于检测化学机械抛光工艺中的谐波振荡并与其反应的方法和控制系统,例如通过采取以下步骤中的至少一个步骤:1)减少或消除谐波振荡; 和2)对抗与谐波振荡相关的噪声。 通过减少或消除谐波振荡,可以使用包括低k电介质膜的具有降低的结构强度的膜。 通过对付噪声,提高了工作环境的质量。

    Mixed LVR and HVR reticle set design for the processing of gate arrays, embedded arrays and rapid chip products
    10.
    发明授权
    Mixed LVR and HVR reticle set design for the processing of gate arrays, embedded arrays and rapid chip products 失效
    混合LVR和HVR光罩组设计用于门阵列,嵌入式阵列和快速芯片产品的处理

    公开(公告)号:US06900075B2

    公开(公告)日:2005-05-31

    申请号:US10699276

    申请日:2003-10-31

    CPC分类号: G03F7/70433

    摘要: An embodiment of the present invention provides a novel method which makes LVR to HVR registration possible by wrapping the X and Y scribes around each instance of each layer on both the LVR and HVR reticles; standard HVR reticles and LVR reticles will not align to one another due to registration and electrical test structures in the scribe being in different locations. Another embodiment of the present invention addresses the loss of die per wafer due to increased sribe area when using LVR and HVR reticles in the same set.

    摘要翻译: 本发明的一个实施例提供了一种新颖的方法,其通过在LVR和HVR光栅两者上的每个层的每个实例周围缠绕X和Y划线器来使得LVR到HVR配准成为可能; 标准的HVR标线片和LVR标线器由于在不同位置的划线器中的配准和电气测试结构而不会彼此对准。 本发明的另一实施例解决了当在同一组中使用LVR和HVR掩模版时,由于增加的采伐面积而导致的晶片损耗。