公开(公告)号：US20070123024A1

公开(公告)日：2007-05-31

申请号：US11290087

申请日：2005-11-30

申请人： Jayanthi Pallinti ,  Dilip Vijay ,  Hemanshu Bhatt ,  Sey-Shing Sun ,  Hong Ying ,  Chiyi Kao ,  Peter Burke ,  Ramaswamy Ranganathan ,  Qwai Low

发明人： Jayanthi Pallinti ,  Dilip Vijay ,  Hemanshu Bhatt ,  Sey-Shing Sun ,  Hong Ying ,  Chiyi Kao ,  Peter Burke ,  Ramaswamy Ranganathan ,  Qwai Low

IPC分类号： H01L21/4763

CPC分类号： H01L21/76801 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.

摘要翻译： 减少或消除引线接合部件中的IMC裂纹问题的不同方法，包括：改变为顶部R 1和R 2的更多的压电绝缘膜; 将顶部钝化膜堆叠更改为更多的压缩膜; 将低k膜改为较高的压缩膜; 降低R层厚度和图案密度以降低拉伸应力; 并最小化退火和介电沉积温度。 每个方法可以单独使用或彼此组合使用以减少Cu / low-k晶片中的总拉伸应力，从而减少或消除了现在在后引线接合部件中看到的IMC裂纹问题。

公开(公告)号：US07531442B2

公开(公告)日：2009-05-12

申请号：US11290087

申请日：2005-11-30

申请人： Jayanthi Pallinti ,  Dilip Vijay ,  Hemanshu Bhatt ,  Sey-Shing Sun ,  Hong Ying ,  Chiyi Kao ,  Peter Burke ,  Ramaswamy Ranganathan ,  Qwai Low

发明人： Jayanthi Pallinti ,  Dilip Vijay ,  Hemanshu Bhatt ,  Sey-Shing Sun ,  Hong Ying ,  Chiyi Kao ,  Peter Burke ,  Ramaswamy Ranganathan ,  Qwai Low

IPC分类号： H01L21/44

CPC分类号： H01L21/76801 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.

摘要翻译： 减少或消除电线接合部件中IMC裂纹问题的不同方式，包括：更换为顶部，R1和R2的更多压电绝缘膜; 将顶部钝化膜堆叠更改为更多的压缩膜; 将低k膜改为较高的压缩膜; 降低R层厚度和图案密度以降低拉伸应力; 并最小化退火和介电沉积温度。 每个方法可以单独使用或彼此组合使用以减少Cu / low-k晶片中的总拉伸应力，从而减少或消除了现在在后引线接合部件中看到的IMC裂纹问题。

公开(公告)号：US08525309B2

公开(公告)日：2013-09-03

申请号：US13173883

申请日：2011-06-30

申请人： Chok Chia ,  Qwai Low ,  Kishor Desai ,  Charles G. Woychik

发明人： Chok Chia ,  Qwai Low ,  Kishor Desai ,  Charles G. Woychik

IPC分类号： H01L23/495 ,  H01L21/50 ,  H01L23/34 ,  H01L21/60 ,  H01R43/16

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/11332 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2224/1339 ,  H01L2224/13401 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2224/8184 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/07811 ,  Y10T29/49204 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/00

摘要： A microelectronic unit can include a lead frame and a device chip. The lead frame can have a plurality of monolithic lead fingers extending in a plane of the lead frame. Each lead finger can have a fan-out portion and a chip connection portion extending in the lead frame plane. The fan-out portions can have first and second opposed surfaces and a first thickness in a first direction between the opposed surfaces. The chip connection portions can have a second thickness smaller than the first thickness. The chip connection portions can define a recess below the first surface. The device chip can have a plurality of at least one of passive devices or active devices. The device chip can have contacts thereon facing the chip connection portions and electrically coupled thereto. At least a portion of a thickness of the device chip can extend within the recess.

摘要翻译： 微电子单元可以包括引线框架和器件芯片。 引线框架可以具有在引线框架的平面中延伸的多个单片引线指。 每个引线指可以具有在引线框架平面中延伸的扇出部分和芯片连接部分。 扇出部分可以在相对的表面之间具有第一和第二相对表面以及在第一方向上的第一厚度。 芯片连接部分可以具有小于第一厚度的第二厚度。 芯片连接部分可以限定第一表面下方的凹陷。 器件芯片可以具有多个无源器件或有源器件中的至少一个。 器件芯片可以具有面向芯片连接部分并且与其电耦合的触点。 装置芯片的厚度的至少一部分可以在凹部内延伸。

公开(公告)号：US08384205B2

公开(公告)日：2013-02-26

申请号：US13174970

申请日：2011-07-01

申请人： Qwai Low ,  Patrick Variot

发明人： Qwai Low ,  Patrick Variot

IPC分类号： H01L23/48

CPC分类号： H01L21/4832 ,  H01L24/45 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/207 ,  Y10S438/928 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/92247 ,  H01L2924/0002

摘要： A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.

摘要翻译： 一种制造电子器件封装的方法。 用第一绝缘层涂覆金属层的第一面并用第二绝缘层涂覆金属层的第二相对侧。 对第一绝缘层进行成形以暴露金属层的第一侧上的接合位置，并且使第二绝缘层图形化，使得第二相对侧上的第二绝缘层的剩余部分位于与第一侧上的接合位置正好相对的位置 。 选择性地去除在第二相对侧上未被第二绝缘层的剩余部分覆盖的金属层的部分，以形成分离的共面金属层。 分离的共面金属层包括结合位置。 选择性地去除第二绝缘层的剩余部分，从而暴露在分离的共面金属层的第二相对侧上的第二接合位置。

公开(公告)号：US20110260324A1

公开(公告)日：2011-10-27

申请号：US13174970

申请日：2011-07-01

申请人： Qwai Low ,  Patrick Variot

发明人： Qwai Low ,  Patrick Variot

IPC分类号： H01L23/49

CPC分类号： H01L21/4832 ,  H01L24/45 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/207 ,  Y10S438/928 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/92247 ,  H01L2924/0002

摘要： A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.

摘要翻译： 一种制造电子器件封装的方法。 用第一绝缘层涂覆金属层的第一面并用第二绝缘层涂覆金属层的第二相对侧。 对第一绝缘层进行成形以暴露金属层的第一侧上的接合位置，并且使第二绝缘层图形化，使得第二相对侧上的第二绝缘层的剩余部分位于与第一侧上的接合位置正好相对的位置 。 选择性地去除在第二相对侧上未被第二绝缘层的剩余部分覆盖的金属层的部分，以形成分离的共面金属层。 分离的共面金属层包括结合位置。 选择性地去除第二绝缘层的剩余部分，从而暴露在分离的共面金属层的第二相对侧上的第二接合位置。

公开(公告)号：US07993981B2

公开(公告)日：2011-08-09

申请号：US12483139

申请日：2009-06-11

申请人： Qwai Low ,  Patrick Variot

发明人： Qwai Low ,  Patrick Variot

IPC分类号： H01L21/00

CPC分类号： H01L21/4832 ,  H01L24/45 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/207 ,  Y10S438/928 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/92247 ,  H01L2924/0002

摘要： A method of manufacturing an electronic device package. Coating a first side of a metallic layer with a first insulating layer and coating a second opposite side of the metallic layer with a second insulating layer. Patterning the first insulating layer to expose bonding locations on the first side of the metallic layer, and patterning the second insulating layer such that remaining portions of the second insulating layer on the second opposite side are located directly opposite to the bonding locations on the first side. Selectively removing portions of the metallic layer that are not covered by the remaining portions of the second insulating layer on the second opposite side to form separated coplanar metallic layers. The separated coplanar metallic layers include the bonding locations. Selectively removing remaining portions of the second insulating layer thereby exposing second bonding locations on the second opposite sides of the separated coplanar metallic layers.

摘要翻译： 一种制造电子器件封装的方法。 用第一绝缘层涂覆金属层的第一面并用第二绝缘层涂覆金属层的第二相对侧。 对第一绝缘层进行成形以暴露金属层的第一侧上的接合位置，并且使第二绝缘层图形化，使得第二相对侧上的第二绝缘层的剩余部分位于与第一侧上的接合位置正好相对的位置 。 选择性地去除在第二相对侧上未被第二绝缘层的剩余部分覆盖的金属层的部分，以形成分离的共面金属层。 分离的共面金属层包括结合位置。 选择性地去除第二绝缘层的剩余部分，从而暴露在分离的共面金属层的第二相对侧上的第二接合位置。

公开(公告)号：US20060113667A1

公开(公告)日：2006-06-01

申请号：US10999423

申请日：2004-11-30

申请人： Chok Chia ,  Qwai Low ,  John McCormick

发明人： Chok Chia ,  Qwai Low ,  John McCormick

IPC分类号： H01L21/44 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/00014 ,  H01L2924/00

摘要： A bond pad structure which improves the reliability of the gold bonds, and thus, of the device. The bond pad structure allows for small gold bonds, which increases the density of the device. One design provides that the aluminum pad is connected to the copper IO strap at one end only. As such, expansion of the aluminum pad is not constrained. Another design provides that a segmented or un-segmented square copper ring is provided under the aluminum pad. There is effectively no copper provided under the aluminum pad in the area under the gold ball band. This reduces the restriction of the expansion of the aluminum pad. Yet another design provides for a reduced copper pad size under the aluminum pad, preferably just large enough for electrical connection.

摘要翻译： 一种接合焊盘结构，其改善了金键的可靠性，从而提高了器件的可靠性。 接合焊盘结构允许小的金键，这增加了器件的密度。 一个设计规定，铝垫仅在一端连接到铜带IO。 因此，铝垫的膨胀不受限制。 另一种设计提供了在铝垫下面的分段或非分段方形铜环。 在金球带下方的铝垫下方没有铜。 这减少了铝垫的膨胀的限制。 另一种设计提供了在铝垫下方的减小的铜垫尺寸，优选地仅仅足够大以进行电连接。

公开(公告)号：US20060055029A1

公开(公告)日：2006-03-16

申请号：US10939082

申请日：2004-09-10

申请人： Maurice Othieno ,  Hong Lim ,  Qwai Low

发明人： Maurice Othieno ,  Hong Lim ,  Qwai Low

IPC分类号： H01L23/34

CPC分类号： H01L23/3735 ,  H01L23/3677 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention is directed toward systems, packages, and methods for providing improved thermal performance in such packages and systems. Embodiments of the invention include a semiconductor integrated circuit (IC) package having a substrate with a heat spreader mounted on the substrate. An IC die is mounted to the heat spreader such that the heat spreader lies in between the die and the substrate. The invention is also directed to a heat spreader plate useable in a semiconductor package. The heat spreader plate comprises a plate comprised of thermally conductive material suitable for attachment to a packaging substrate wherein the plate includes openings for exposing electrical bonding surfaces of a packaging substrate when the heater spreader plate is mounted on the packaging substrate. Such openings enable wirebonding between the exposed electrical bonding surfaces of the substrate and an integrated circuit die to complete construction of a package including the heatspreader.

摘要翻译： 本发明涉及用于在这种包装和系统中提供改进的热性能的系统，包装和方法。 本发明的实施例包括具有安装在基板上的散热器的基板的半导体集成电路（IC）封装。 IC散热器安装在散热器上，使得散热器位于模具和基板之间。 本发明还涉及可用于半导体封装的散热板。 散热板包括由适于附接到包装基板的导热材料构成的板，其中，当加热器散布板安装在包装基板上时，该板包括用于暴露包装基板的电接合表面的开口。 这种开口使得能够在基板的暴露的电接合表面和集成电路管芯之间进行引线接合，以完成包括散热器的封装的构造。

公开(公告)号：US20050281011A1

公开(公告)日：2005-12-22

申请号：US10873387

申请日：2004-06-22

申请人： Hong Lim ,  Maurice Othieno ,  Qwai Low

发明人： Hong Lim ,  Maurice Othieno ,  Qwai Low

IPC分类号： H01L23/31 ,  H01L23/433 ,  H05K1/18

CPC分类号： H01L23/4334 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit (IC) package comprises a package substrate, an IC die mounted on the package substrate, a wire bond electrically connecting the IC die and the package substrate, and a heat spreader mounted on the package substrate. The heat spreader comprises a hole through a portion thereof. The IC die and the wire bond are disposed substantially between the heat spreader and the package substrate.

摘要翻译： 集成电路（IC）封装包括封装基板，安装在封装基板上的IC管芯，将IC芯片与封装基板电连接的引线键合件和安装在封装基板上的散热器。 散热器包括穿过其一部分的孔。 IC芯片和引线接合件基本上设置在散热器和封装衬底之间。

公开(公告)号：US20130001757A1

公开(公告)日：2013-01-03

申请号：US13173883

申请日：2011-06-30

申请人： Chok Chia ,  Qwai Low ,  Kishor Desai ,  Charles G. Woychik

发明人： Chok Chia ,  Qwai Low ,  Kishor Desai ,  Charles G. Woychik

IPC分类号： H01L23/495 ,  H01R43/16 ,  H01L21/50 ,  H01L23/34 ,  H01L21/60

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/11332 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13339 ,  H01L2224/13347 ,  H01L2224/1339 ,  H01L2224/13401 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81192 ,  H01L2224/8184 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/07811 ,  Y10T29/49204 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/00

摘要： A microelectronic unit can include a lead frame and a device chip. The lead frame can have a plurality of monolithic lead fingers extending in a plane of the lead frame. Each lead finger can have a fan-out portion and a chip connection portion extending in the lead frame plane. The fan-out portions can have first and second opposed surfaces and a first thickness in a first direction between the opposed surfaces. The chip connection portions can have a second thickness smaller than the first thickness. The chip connection portions can define a recess below the first surface. The device chip can have a plurality of at least one of passive devices or active devices. The device chip can have contacts thereon facing the chip connection portions and electrically coupled thereto. At least a portion of a thickness of the device chip can extend within the recess.

摘要翻译： 微电子单元可以包括引线框架和器件芯片。 引线框架可以具有在引线框架的平面中延伸的多个单片引线指。 每个引线指可以具有在引线框架平面中延伸的扇出部分和芯片连接部分。 扇出部分可以在相对的表面之间具有第一和第二相对表面以及在第一方向上的第一厚度。 芯片连接部分可以具有小于第一厚度的第二厚度。 芯片连接部分可以限定第一表面下方的凹陷。 器件芯片可以具有多个无源器件或有源器件中的至少一个。 器件芯片可以具有面向芯片连接部分并且与其电耦合的触点。 装置芯片的厚度的至少一部分可以在凹部内延伸。