Invention Grant
- Patent Title: Manufacturing method of semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件的制造方法
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Application No.: US11448071Application Date: 2006-06-07
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Publication No.: US07534629B2Publication Date: 2009-05-19
- Inventor: Teruo Shoji , Akio Hasebe , Yoshinori Deguchi , Motoji Murakami , Masayoshi Okamoto , Yasunori Narizuka , Susumu Kasukabe
- Applicant: Teruo Shoji , Akio Hasebe , Yoshinori Deguchi , Motoji Murakami , Masayoshi Okamoto , Yasunori Narizuka , Susumu Kasukabe
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2005-168112 20050608
- Main IPC: H01L21/66
- IPC: H01L21/66

Abstract:
By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.
Public/Granted literature
- US20060281222A1 Manufacturing method of semiconductor integrated circuit device Public/Granted day:2006-12-14
Information query
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