Invention Grant
US07659838B2 Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits
有权
用于可编程逻辑器件集成电路上的高速串行数据接收器的解串器电路
- Patent Title: Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits
- Patent Title (中): 用于可编程逻辑器件集成电路上的高速串行数据接收器的解串器电路
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Application No.: US11359273Application Date: 2006-02-21
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Publication No.: US07659838B2Publication Date: 2010-02-09
- Inventor: Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Tim Tri Hoang , Ramanand Venkata , Chong Lee
- Applicant: Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Tim Tri Hoang , Ramanand Venkata , Chong Lee
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Ropes & Gray LLP
- Agent Robert R. Jackson
- Main IPC: H03M9/00
- IPC: H03M9/00
Abstract:
Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
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