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10 条记录 (耗时 0.013 秒)

    Multiple channel bonding in a high speed clock network
    1.
    发明授权
    Multiple channel bonding in a high speed clock network 有权
    在高速时钟网络中进行多信道绑定

    公开(公告)号：US08464088B1

    公开(公告)日：2013-06-11

    申请号：US12915794

    申请日：2010-10-29

    申请人： Toan Thanh Nguyen ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Weiqi Ding ,  Thungoc M. Tran

    发明人： Toan Thanh Nguyen ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Weiqi Ding ,  Thungoc M. Tran

    IPC分类号： G06F1/04

    CPC分类号： G06F1/04 ,  G06F1/10

    摘要： Various methods and structures related to clock distribution for flexible channel bonding are disclosed. One embodiment provides a clock network in physical media attachment (“PMA”) circuitry, a specific type or portion of system interconnect circuitry, arranged in pairs of channel groups. In one embodiment, clock generation circuitry blocks (“CGBs”) in each pair of channel groups receives outputs of multiple phased locked loop circuits (“PLLs”) which can be selectively utilized by the CGBs to generate PMA clock signals. In another embodiment, the CGBs can also select output of a clock data recovery (“CDR”)/transmit PLL circuitry block in one of the channels of a channel group of the pair of channel groups. In one embodiment, first groups of connection lines couple circuitry in a channel group pair such that a designated CGB in each channel group pair can provide clock signals to one or more of the channels in the channel group pair. In one embodiment, second groups of connection lines connect channels in one channel group pair to channels in other channel group pairs such that one or more channels across the channel group pairs can receive a clock signal generated by a CGB in a designated channel. These and other embodiments are described more fully in the disclosure.

    摘要翻译： 公开了与用于柔性通道结合的时钟分配有关的各种方法和结构。 一个实施例提供物理介质连接（“PMA”）电路中的时钟网络，系统互连电路的特定类型或部分，被布置成成对的信道组。 在一个实施例中，每对信道组中的时钟产生电路块（“CGB”）接收多个锁相环电路（“PLL”）的输出，这些电路可被CGB选择性地用于产生PMA时钟信号。 在另一个实施例中，CGB还可以在一对信道组的信道组的信道之一中选择时钟数据恢复（“CDR”）/发送PLL电路块的输出。 在一个实施例中，第一组连接线将信道组对中的电路耦合，使得每个信道组对中的指定CGB可以向信道组对中的一个或多个信道提供时钟信号。 在一个实施例中，第二组连接线将一个信道组对中的信道与其它信道组对中的信道相连，使得跨信道组对的一个或多个信道可以接收由指定信道中的CGB产生的时钟信号。 在本公开中更全面地描述了这些和其它实施例。

    Techniques for canceling offsets in differential circuits
    5.
    发明授权
    Techniques for canceling offsets in differential circuits 有权
    差分电路消除偏移的技术

    公开(公告)号：US07863941B1

    公开(公告)日：2011-01-04

    申请号：US12365585

    申请日：2009-02-04

    申请人： Toan Thanh Nguyen ,  Thungoc M. Tran ,  Sergey Shumarayev

    发明人： Toan Thanh Nguyen ,  Thungoc M. Tran ,  Sergey Shumarayev

    IPC分类号： H03K5/22

    CPC分类号： H03K3/356139 ,  G11C7/065

    摘要： A circuit includes a differential circuit that generates a differential output signal at first and second output nodes. The circuit also includes a first variable capacitor coupled to the first output node of the differential circuit, and a second variable capacitor coupled to the second output node of the differential circuit. A control circuit controls capacitances of the first and the second variable capacitors in response to a measurement of the differential output signal.

    摘要翻译： 电路包括在第一和第二输出节点处产生差分输出信号的差分电路。 电路还包括耦合到差分电路的第一输出节点的第一可变电容器和耦合到差分电路的第二输出节点的第二可变电容器。 响应于差分输出信号的测量，控制电路控制第一和第二可变电容器的电容。

    Differential bang-bang phase detector (BBPD) with latency reduction
    7.
    发明授权
    Differential bang-bang phase detector (BBPD) with latency reduction 有权
    差分波浪相位检测器（BBPD）具有延迟降低

    公开(公告)号：US07482841B1

    公开(公告)日：2009-01-27

    申请号：US11731463

    申请日：2007-03-29

    申请人： Toan Thanh Nguyen ,  Thungoc M. Tran

    发明人： Toan Thanh Nguyen ,  Thungoc M. Tran

    IPC分类号： H03D13/00

    CPC分类号： H03D13/004

    摘要： Bang-bang phase detection (BBPD) methods and circuits are presented for providing low latency, low jitter phase detection for use in high data-rate applications. A shortened data-path implementation of BBPD methods and circuits provides low-latency production of two output signals including alternating samples of the input signal. Combinational logic circuitry is also provided to produce a clock-data recovery (CDR) signal indicative of the phase of the input signal with respect to a clock signal. The use of differential signals throughout the BBPD timing circuitry provides for the production of a low jitter CDR signal.

    摘要翻译： 提出了Bang-bang相位检测（BBPD）方法和电路，用于提供低延迟，低抖动相位检测，用于高数据速率应用。 BBPD方法和电路的缩短的数据路径实现提供了低延迟生成两个输出信号，包括输入信号的交替采样。 还提供组合逻辑电路以产生指示相对于时钟信号的输入信号的相位的时钟数据恢复（CDR）信号。 在整个BBPD定时电路中使用差分信号提供低抖动CDR信号的产生。

    Leakage compensation in dynamic flip-flop
    9.
    发明授权
    Leakage compensation in dynamic flip-flop 有权
    动态触发器中的泄漏补偿

    公开(公告)号：US07777529B1

    公开(公告)日：2010-08-17

    申请号：US11269456

    申请日：2005-11-07

    申请人： Toan Thanh Nguyen ,  Thungoc M. Tran

    发明人： Toan Thanh Nguyen ,  Thungoc M. Tran

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/412 ,  H03K19/0008

    摘要： A dynamic flip-flop includes a leakage compensation circuit enabling operation over a wide range of frequencies. Nodes of the dynamic flip-flop store the flip-flop's state. The leakage compensation circuit drains leakage currents from these nodes to prevent the node voltage from rising and triggering an erroneous state change when a data signal changes in the middle of the clock cycle. The leakage compensation circuit associated with a node is activated when the node is set to a low logic level voltage. The leakage compensation circuit is adapted to draw a current from a node that compensates for the leakage current supplied to the node. At the least, this current draw is sufficient to prevent the voltage at the node from rising above a state change threshold voltage during the time period between refresh operations.

    摘要翻译： 动态触发器包括允许在宽范围的频率上操作的漏电补偿电路。 动态触发器的节点存储触发器的状态。 当数据信号在时钟周期的中间改变时，泄漏补偿电路从这些节点漏出漏电流，以防止节点电压上升并触发错误状态改变。 当节点设置为低逻辑电平电压时，与节点相关联的漏电补偿电路被激活。 泄漏补偿电路适于从节点抽取电流来补偿提供给节点的漏电流。 至少，这种电流消耗足以防止在刷新操作期间节点处的电压升高到高于状态变化阈值电压。

    Integrated circuit serializers with two-phase global master clocks
    10.
    发明授权
    Integrated circuit serializers with two-phase global master clocks 有权
    具有两相全球主时钟的集成电路串行器

    公开(公告)号：US07245240B1

    公开(公告)日：2007-07-17

    申请号：US11370727

    申请日：2006-03-07

    申请人： Toan Thanh Nguyen ,  Thungoc M. Tran ,  Sergey Shumarayev

    发明人： Toan Thanh Nguyen ,  Thungoc M. Tran ,  Sergey Shumarayev

    IPC分类号： H03M9/00

    CPC分类号： H03M9/00 ,  H03K5/135 ,  H03K5/15013

    摘要： Integrated circuit serializer circuitry is provided that converts parallel data to serial data on an integrated circuit. A two-phase global serializer master clock generator uses a four-phase internal clock to generate a two-phase global serializer master clock. The two-phase global serializer master clock is distributed globally on the integrated circuit using a distribution path. The integrated circuit has multiple serial communications channels each of which has an associated serializer. Each serializer contains circuitry that derives a number of clock signals from the two phases of the global serializer master clock. Each serializer uses the derived clocks in converting parallel data to serial data for transmission over its associated serial communications channel. The serializers each contain two smaller serializers that convert first and second sets of parallel data to first and second serial outputs. A 2:1 serializer in each serializer merges the first and second serial outputs.

    摘要翻译： 提供集成电路串行化器电路，其将并行数据转换为集成电路上的串行数据。 两相全局串行器主时钟发生器使用四相内部时钟来生成两相全局串行器主时钟。 两相全局串行器主时钟使用分布路径全局分布在集成电路上。 集成电路具有多个串行通信通道，每个通道具有相关联的串行器。 每个串行器包含从全局串行器主时钟的两个相位导出多个时钟信号的电路。 每个串行器使用派生时钟将并行数据转换为串行数据，以便通过其相关联的串行通信通道进行传输。 串行器每个都包含两个较小的串行器，它们将第一和第二组并行数据转换为第一和第二串行输出。 每个串行器中的2：1串行器合并第一个和第二个串行输出。