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    Multi-channel communication circuitry for programmable logic device integrated circuits and the like
    5.
    发明授权
    Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
    用于可编程逻辑器件集成电路等的多通道通信电路

    公开(公告)号：US07656187B2

    公开(公告)日：2010-02-02

    申请号：US11288810

    申请日：2005-11-28

    申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

    发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.

    摘要翻译： 诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。 提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作 一起，八个渠道在一起等）。 共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。 电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以便于诸如电路设计和验证之类的事情。

    Clock circuitry for programmable logic devices
    6.
    发明授权
    Clock circuitry for programmable logic devices 有权
    可编程逻辑器件的时钟电路

    公开(公告)号：US07276936B1

    公开(公告)日：2007-10-02

    申请号：US11239702

    申请日：2005-09-29

    申请人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  In Whan Kim ,  Thungoc Tran

    发明人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  In Whan Kim ,  Thungoc Tran

    IPC分类号： H03K19/00

    CPC分类号： H03K19/1774 ,  H03K19/17744

    摘要： A programmable logic device includes high-speed serial interface (“HSSI”) circuitry that employs one or more clock signals. In addition to use of these clock signals in the HSSI circuitry, circuitry is provided for allowing at least one of these signals to be distributed throughout the PLD core circuitry, e.g., for use as an additional clock signal in the PLD core. Clock distribution is preferably done in a low-skew way.

    摘要翻译： 可编程逻辑器件包括采用一个或多个时钟信号的高速串行接口（“HSSI”）电路。 除了在HSSI电路中使用这些时钟信号之外，提供电路以允许这些信号中的至少一个分布在整个PLD核心电路中，例如用作PLD核心中的附加时钟信号。 时钟分布优选以低偏斜方式进行。

    Modular buffering circuitry for multi-channel transceiver clock and other signals
    7.
    发明授权
    Modular buffering circuitry for multi-channel transceiver clock and other signals 有权
    用于多通道收发器时钟和其他信号的模块化缓冲电路

    公开(公告)号：US07304507B1

    公开(公告)日：2007-12-04

    申请号：US11288496

    申请日：2005-11-28

    申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang

    发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang

    IPC分类号： H03K19/00

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： Circuitry for distributing signals such as reference clock signals among blocks of transceiver circuitry on an integrated circuit such as a field programmable gate array (“FPGA”) employs bidirectional buffers rather than unidirectional buffers. This allows all buffers to have the same construction regardless of physical location, which facilitates construction of the circuitry using identical or substantially identical modules. The same approach may be used for distributing other types of signals among the transceiver blocks. For example, this approach may be used for distributing calibration control signals.

    摘要翻译： 在集成电路（例如现场可编程门阵列（“FPGA”）上的收发器电路块之间分配诸如参考时钟信号的信号的电路采用双向缓冲器而不是单向缓冲器。 这允许所有缓冲器具有相同的结构，而不管物理位置如何，这有助于使用相同或基本相同的模块构建电路。 相同的方法可以用于在收发器块之间分配其他类型的信号。 例如，该方法可用于分配校准控制信号。

    Receiver equalizer circuitry having wide data rate and input common mode voltage ranges
    8.
    发明授权
    Receiver equalizer circuitry having wide data rate and input common mode voltage ranges 有权
    接收机均衡器电路具有宽数据速率和输入共模电压范围

    公开(公告)号：US08222967B1

    公开(公告)日：2012-07-17

    申请号：US12644128

    申请日：2009-12-22

    申请人： Sangeeta Raman ,  Tim Tri Hoang ,  Sergey Yuryevich Shumarayev

    发明人： Sangeeta Raman ,  Tim Tri Hoang ,  Sergey Yuryevich Shumarayev

    IPC分类号： H03H7/30 ,  H03F3/45

    CPC分类号： H03F3/45192 ,  H03F3/193 ,  H03F3/45197 ,  H03F3/45475 ,  H03F3/72 ,  H03F2200/405 ,  H03F2203/45488 ,  H03F2203/45494 ,  H03F2203/45686 ,  H03F2203/7236 ,  H03H11/1213 ,  H03H11/48

    摘要： Equalizer circuitry on an integrated circuit (“IC”) includes a plurality of NMOS equalizer stages connected in series. Each NMOS stage may include folded active inductor circuitry. Each NMOS stage may also include various circuit elements having controllably variable circuit parameters so that the equalizer can be controllably adapted to perform for any of a wide range of high-speed serial data signal bit rates and other variations of communication protocols and/or communication conditions. For example, each NMOS stage may be programmable to control at least one of bandwidth and power consumption of the equalizer circuitry. The equalizer may also have a first PMOS stage that can be used instead of the first NMOS stage in cases in which the voltage of the incoming signal to be equalized is too low for an initial NMOS stage.

    摘要翻译： 集成电路（“IC”）上的均衡器电路包括串联连接的多个NMOS均衡器级。 每个NMOS级可包括折叠的有源电感电路。 每个NMOS级还可以包括具有可控制的可变电路参数的各种电路元件，使得均衡器可被可控地适用于执行宽范围的高速串行数据信号比特率和通信协议和/或通信条件的其它变化 。 例如，每个NMOS级可以是可编程的，以控制均衡器电路的带宽和功耗中的至少一个。 在均衡的输入信号的电压对于初始NMOS级来说太低的情况下，均衡器也可以具有第一PMOS级，而不用第一NMOS级。

    Wide range and dynamically reconfigurable clock data recovery architecture
    10.
    发明授权
    Wide range and dynamically reconfigurable clock data recovery architecture 有权
    宽范围和动态可重构的时钟数据恢复架构

    公开(公告)号：US08189729B2

    公开(公告)日：2012-05-29

    申请号：US11329197

    申请日：2006-01-09

    申请人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  Wilson Wong ,  Rakesh Patel

    发明人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  Wilson Wong ,  Rakesh Patel

    IPC分类号： H04L7/00

    CPC分类号： H03L7/087 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/10 ,  H04L7/0004 ,  H04L7/033

    摘要： Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.

    摘要翻译： 宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。 为了支持广泛的数据速率，CDR架构包括多个操作参数。 这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。 可以在不关闭电路或PLD的情况下动态重新编程参数。 这允许CDR电路在各种标准和协议之间进行即时切换。