发明授权
US07671362B2 Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing
失效
用于确定双镶嵌加工的最佳种子和衬层层厚度的测试结构
- 专利标题： Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing
- 专利标题（中）： 用于确定双镶嵌加工的最佳种子和衬层层厚度的测试结构
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申请号： US11953568申请日： 2007-12-10
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公开(公告)号： US07671362B2公开(公告)日： 2010-03-02
- 发明人: Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
- 申请人： Tibor Bolom , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Paul S. McLaughlin , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert , James Werking
- 申请人地址： US NY Armonk US CA Sunnyvale
- 专利权人： International Business Machines Corporation,Advanced Micro Devices, Inc. (AMD)
- 当前专利权人： International Business Machines Corporation,Advanced Micro Devices, Inc. (AMD)
- 当前专利权人地址： US NY Armonk US CA Sunnyvale
- 代理机构： Cantor Colburn LLP
- 代理商 Wenjie Li
- 主分类号： H01L23/58
- IPC分类号： H01L23/58
摘要：
A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.
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