发明授权
US07689772B2 Power-performance modulation in caches using a smart least recently used scheme
失效
使用智能最近最近使用的方案在高速缓存中进行功率性能调制
- 专利标题： Power-performance modulation in caches using a smart least recently used scheme
- 专利标题（中）： 使用智能最近最近使用的方案在高速缓存中进行功率性能调制
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申请号： US11418883申请日： 2006-05-04
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公开(公告)号： US07689772B2公开(公告)日： 2010-03-30
- 发明人: Satish Damaraju , Subramaniam Maiyuran , Truyen Trinh , Parag Raval , Peter Smith
- 申请人： Satish Damaraju , Subramaniam Maiyuran , Truyen Trinh , Parag Raval , Peter Smith
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理商 Caroline M. Fleming
- 主分类号： G06F12/00
- IPC分类号： G06F12/00 ; G06F13/00
摘要：
The number of ways in an N-way set associative sequential cache is modulated to trade power and performance. Way selection is restricted during the allocation based on address so that only a subset of the N-ways is used for a range of addresses allowing the N-ways that are not in use to be powered off.