发明授权
US07718496B2 Techniques for enabling multiple Vt devices using high-K metal gate stacks
失效
使用高K金属栅极堆叠实现多个Vt器件的技术
- 专利标题: Techniques for enabling multiple Vt devices using high-K metal gate stacks
- 专利标题(中): 使用高K金属栅极堆叠实现多个Vt器件的技术
-
申请号: US11927964申请日: 2007-10-30
-
公开(公告)号: US07718496B2公开(公告)日: 2010-05-18
- 发明人: Martin M. Frank , Arvind Kumar , Vijay Narayanan , Vamsi K. Paruchuri , Jeffrey Sleight
- 申请人: Martin M. Frank , Arvind Kumar , Vijay Narayanan , Vamsi K. Paruchuri , Jeffrey Sleight
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Michael J. Chang, LLC
- 代理商 Vazken Alexanian
- 主分类号: H01L21/8234
- IPC分类号: H01L21/8234 ; H01L21/8244
摘要:
Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.