公开(公告)号：US09202698B2

公开(公告)日：2015-12-01

申请号：US13406784

申请日：2012-02-28

申请人： Hemanth Jagannathan ,  Vamsi K. Paruchuri

发明人： Hemanth Jagannathan ,  Vamsi K. Paruchuri

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L23/485 ,  H01L29/51 ,  H01L21/84

CPC分类号： H01L21/28229 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/485 ,  H01L27/092 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV.

摘要翻译： 可以通过在替代栅极方案中提供具有不同厚度的导电金属氮化物层来提供具有不同功函数的栅电极。 在去除一次性栅极结构和形成栅极电介质层时，至少一个增量厚度的导电金属氮化物层被添加到一些栅极空腔内，而不被添加到一些其它栅极腔中。 随后添加最小厚度的导电金属氮化物层作为连续层。 如此形成的导电金属氮化物层在不同的栅腔上具有不同的厚度。 沉积栅极填充导电材料层，并执行平面化以提供具有不同导电金属氮化物层厚度的多个栅电极。 导电金属氮化物层的不同厚度可以提供具有约400mV范围的不同功函数。

公开(公告)号：US08753936B2

公开(公告)日：2014-06-17

申请号：US12190220

申请日：2008-08-12

申请人： Michael P. Chudzik ,  Martin M. Frank ,  Herbert L. Ho ,  Mark J. Hurley ,  Rashmi Jha ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

发明人： Michael P. Chudzik ,  Martin M. Frank ,  Herbert L. Ho ,  Mark J. Hurley ,  Rashmi Jha ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8234

CPC分类号： H01L29/49 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4958 ,  H01L29/517

摘要： Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.

摘要翻译： 提出了离子注入来改变双功能金属栅极整合的有效功函数。 一种方法可以包括在第一类型场效应晶体管（FET）区域和第二类型FET区域上形成高介电常数（高k）层; 在第一型FET区域和第二类型FET区域上形成具有与第一型FET兼容的第一有效功函数的金属层; 以及通过在第二类型FET区域上将金属注入到金属层中，将第一有效功函数改变为第二类不同的有效功函数。

公开(公告)号：US08680623B2

公开(公告)日：2014-03-25

申请号：US13433815

申请日：2012-03-29

申请人： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

发明人： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

IPC分类号： H01L21/8244 ,  H01L21/70

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108

摘要： Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

摘要翻译： 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

公开(公告)号：US08658501B2

公开(公告)日：2014-02-25

申请号：US12535383

申请日：2009-08-04

申请人： Supratik Guha ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Supratik Guha ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8234

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： In one embodiment, the invention is a method and apparatus for flatband voltage tuning of high-k field effect transistors. One embodiment of a field effect transistor includes a substrate, a high-k dielectric layer deposited on the substrate, a gate electrode deposited on the high-k dielectric layer, and a dipole layer positioned between the substrate and the gate electrode, for shifting the threshold voltage of the field effect transistor.

摘要翻译： 在一个实施例中，本发明是用于高k场效应晶体管的平带电压调谐的方法和装置。 场效应晶体管的一个实施例包括衬底，沉积在衬底上的高k电介质层，沉积在高k电介质层上的栅电极和位于衬底和栅电极之间的偶极子层，用于使 场效应晶体管的阈值电压。

公开(公告)号：US20130217220A1

公开(公告)日：2013-08-22

申请号：US13608310

申请日：2012-09-10

申请人： Hemanth Jagannathan ,  Vamsi K. Paruchuri

发明人： Hemanth Jagannathan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/283

CPC分类号： H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： A tantalum alloy layer is employed as a work function metal for field effect transistors. The tantalum alloy layer can be selected from TaC, TaAl, and TaAlC. When used in combination with a metallic nitride layer, the tantalum alloy layer and the metallic nitride layer provides two work function values that differ by 300 mV˜500 mV, thereby enabling multiple field effect transistors having different threshold voltages. The tantalum alloy layer can be in contact with a first gate dielectric in a first gate, and the metallic nitride layer can be in contact with a second gate dielectric having a same composition and thickness as the first gate dielectric and located in a second gate.

公开(公告)号：US08383483B2

公开(公告)日：2013-02-26

申请号：US12541562

申请日：2009-08-14

申请人： John C. Arnold ,  Glenn A. Biery ,  Alessandro C. Callegari ,  Tze-Chiang Chen ,  Michael P. Chudzik ,  Bruce B. Doris ,  Michael A. Gribelyuk ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Joseph S. Newbury ,  Vamsi K. Paruchuri ,  Michelle L. Steen

发明人： John C. Arnold ,  Glenn A. Biery ,  Alessandro C. Callegari ,  Tze-Chiang Chen ,  Michael P. Chudzik ,  Bruce B. Doris ,  Michael A. Gribelyuk ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Joseph S. Newbury ,  Vamsi K. Paruchuri ,  Michelle L. Steen

IPC分类号： H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.

摘要翻译： 本发明涉及互补金属氧化物半导体（CMOS）电路，其各自包含至少第一和第二栅极堆叠。 第一栅极堆叠位于半导体衬底中的第一器件区域（例如，n-FET器件区域）上，并且至少从底部至顶部包括栅极介电层，金属栅极导体和含硅的 门导体。 第二栅极堆叠位于半导体衬底中的第二器件区域（例如，p-FET器件区域）上，并且至少包括从栅极电介质层和含硅栅极导体的底部到顶部。 可以通过本发明的各种方法以集成的方式在半导体衬底上形成第一和第二栅极叠层。

公开(公告)号：US20120318666A1

公开(公告)日：2012-12-20

申请号：US13561599

申请日：2012-07-30

申请人： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

发明人： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

IPC分类号： C25D19/00

CPC分类号： C25D5/18 ,  C25D5/024 ,  C25D17/001 ,  C25D17/002 ,  C25D17/005 ,  H01L21/2885 ,  H01L21/7624

摘要： An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane.

摘要翻译： 提供了一种用于在晶片的表面上沉积金属层的电镀设备和方法，其中所述设备和方法不需要将电极物理附接到晶片。 要镀覆的晶片的表面被定位成面对阳极，并且在晶片和电极之间设置电镀液以产生局部金属电镀。 晶片可以被定位成物理分离并且位于阳极和阴极之间，使得面向阳极的晶片的一侧包含阴极电解液，并且晶片的面向阴极的另一侧包含阳极电解液。 或者，阳极和阴极可以存在于同一电镀液中晶片的同一侧。 在一个实例中，阳极和阴极被半透膜隔开。

公开(公告)号：US20120270385A1

公开(公告)日：2012-10-25

申请号：US13536366

申请日：2012-06-28

申请人： Nestor A. Bojarczuk ,  Michael P. Chudzik ,  Matthew W. Copel ,  Supratik Guha ,  Richard A. Haight ,  Vijay Narayanan ,  Martin P. O'Boyle ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk ,  Michael P. Chudzik ,  Matthew W. Copel ,  Supratik Guha ,  Richard A. Haight ,  Vijay Narayanan ,  Martin P. O'Boyle ,  Vamsi K. Paruchuri

IPC分类号： H01L21/28

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/51

摘要： A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.

摘要翻译： 场效应晶体管（FET）包括至少部分地设置在身体区域中的体区和源区。 FET还包括至少部分地设置在体区中的漏极区域和氮氧化钼（MoNO）栅极。 FET还包括具有高介电常数（k）的电介质，其布置在体区和MoNO门之间。

公开(公告)号：US20110165767A1

公开(公告)日：2011-07-07

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/28

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US07833849B2

公开(公告)日：2010-11-16

申请号：US11323564

申请日：2005-12-30

申请人： Alessandro C. Callegari ,  Tze-Chiang Chen ,  Michael P. Chudzik ,  Bruce B. Doris ,  Young-Hee Kim ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen ,  Ying Zhang

发明人： Alessandro C. Callegari ,  Tze-Chiang Chen ,  Michael P. Chudzik ,  Bruce B. Doris ,  Young-Hee Kim ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen ,  Ying Zhang

IPC分类号： H01L21/62

CPC分类号： H01L21/823857 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of fabricating semiconductor structure is provided in which at least one nFET device and a least one pFET device are formed on a semiconductor substrate. Each device region formed includes a dielectric stack that has a net dielectric constant equal to or greater than silicon dioxide. Gate stacks are provided on each of the dielectric stacks, wherein one of the gate stacks includes a metal gate electrode located atop a surface of a thinned polygate electrode.

摘要翻译： 提供一种制造半导体结构的方法，其中至少一个nFET器件和至少一个pFET器件形成在半导体衬底上。 形成的每个器件区域包括具有等于或大于二氧化硅的净介电常数的电介质叠层。 在每个电介质堆叠上设置栅极堆叠，其中栅极堆叠中的一个包括位于变薄的多晶硅电极的表面顶部的金属栅电极。