发明授权
US07723235B2 Method for smoothing a resist pattern prior to etching a layer using the resist pattern
失效
在使用抗蚀剂图案蚀刻层之前使抗蚀剂图案平坦化的方法
- 专利标题： Method for smoothing a resist pattern prior to etching a layer using the resist pattern
- 专利标题（中）： 在使用抗蚀剂图案蚀刻层之前使抗蚀剂图案平坦化的方法
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申请号： US11571853申请日： 2005-06-10
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公开(公告)号： US07723235B2公开(公告)日： 2010-05-25
- 发明人: Masaru Kurihara , Masaru Izawa
- 申请人： Masaru Kurihara , Masaru Izawa
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Antonelli, Terry, Stout & Kraus, LLP.
- 优先权： JP2004-270670 20040917
- 国际申请： PCT/JP2005/013230 WO 20050610
- 国际公布： WO2006/030581 WO 20060323
- 主分类号： H01L21/311
- IPC分类号： H01L21/311 ; H01L21/3065
摘要：
After a polycrystalline silicon film (5) is formed on a semiconductor substrate via an insulating film for a gate insulating film (step S1), an organic antireflection film (21) is formed on the polycrystalline silicon film (5) (step S2), and a resist pattern (22) is formed on the antireflection film (21) (step S3). Then, a passivation film (23) is deposited on the antireflection film (21) so as to cover the resist pattern (22) by plasma using fluorocarbon gas while a bias voltage is being applied to the semiconductor substrate (step S4). Then, the passivation film (23) and the antireflection film (21) are etched by plasma using gas containing oxygen gas (step S5). Thereafter, the polycrystalline silicon film (5) is etched using the resist pattern (22) with reduced line edge roughness as an etching mask to form a gate electrode (step S6).
公开/授权文献
- US20080045022A1 Semiconductor Device Manufacturing Method 公开/授权日：2008-02-21
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