发明授权
- 专利标题: Semiconductor device package structure
- 专利标题(中): 半导体器件封装结构
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申请号: US12235734申请日: 2008-09-23
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公开(公告)号: US07723835B2公开(公告)日: 2010-05-25
- 发明人: Moriyoshi Nakashima , Kazuo Kobayashi , Natsuo Ajika
- 申请人: Moriyoshi Nakashima , Kazuo Kobayashi , Natsuo Ajika
- 申请人地址: JP Hyogo
- 专利权人: GENUSION, Inc.
- 当前专利权人: GENUSION, Inc.
- 当前专利权人地址: JP Hyogo
- 代理机构: Renner, Otto, Boisselle & Sklar, LLP
- 优先权: JP2003-359896 20031020
- 主分类号: H01L23/02
- IPC分类号: H01L23/02
摘要:
A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11′). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.
公开/授权文献
- US20090065922A1 SEMICONDUCTOR DEVICE PACKAGE STRUCTURE 公开/授权日:2009-03-12
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