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1.发明授权公开(公告)号：US08044498B2
公开(公告)日：2011-10-25
申请号：US12164503
申请日：2008-06-30
IPC分类号： H01L23/07
CPC分类号： H01L25/0657 , H01L2224/48145 , H01L2224/48227 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2225/06575 , H01L2225/06596 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012
摘要： A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on.Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.
摘要翻译： 可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。 使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。 提供给半导体芯片安装的密封子板的突起附接到封装基板。 多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。
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公开(公告)号：US20080265433A1
公开(公告)日：2008-10-30
申请号：US12164503
申请日：2008-06-30
IPC分类号： H01L23/49
CPC分类号： H01L25/0657 , H01L2224/48145 , H01L2224/48227 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2225/06575 , H01L2225/06596 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012
摘要： A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on.Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.
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3.发明授权公开(公告)号：US07420206B2
公开(公告)日：2008-09-02
申请号：US11456913
申请日：2006-07-12
IPC分类号： H01L29/10
CPC分类号： H01L25/0657 , H01L2224/48145 , H01L2224/48227 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2225/06575 , H01L2225/06596 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012
摘要： A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.
摘要翻译： 可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。 使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。 提供给半导体芯片安装的密封子板的突起附接到封装基板。 多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。
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4.发明申请公开(公告)号：US20080121878A1
公开(公告)日：2008-05-29
申请号：US11456913
申请日：2006-07-12
CPC分类号： H01L25/0657 , H01L2224/48145 , H01L2224/48227 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2225/06575 , H01L2225/06596 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012
摘要： A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on.Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.
摘要翻译： 可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。 使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。 提供给半导体芯片安装的密封子板的突起附接到封装基板。 多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。
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5.发明申请公开(公告)号：US20110074045A2
公开(公告)日：2011-03-31
申请号：US12164503
申请日：2008-06-30
IPC分类号： H01L23/49
CPC分类号： H01L25/0657 , H01L2224/48145 , H01L2224/48227 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2225/06575 , H01L2225/06596 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012
摘要： A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on. Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.
摘要翻译： 可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。 使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。 提供给半导体芯片安装的密封子板的突起附接到封装基板。 多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。
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公开(公告)号：US20090065922A1
公开(公告)日：2009-03-12
申请号：US12235734
申请日：2008-09-23
IPC分类号： H01L23/02
CPC分类号： H01L23/3135 , H01L23/3128 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2225/0651 , H01L2225/06513 , H01L2225/0652 , H01L2225/06572 , H01L2225/06582 , H01L2225/06596 , H01L2924/00014 , H01L2924/01004 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11′). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.
摘要翻译： 半导体芯片安装插入件（60）通过在半导体芯片（50）和插入件（20）之间执行引线键合而构成，其中连接到芯片（50）的端子（51）的端子（21）和分离的端子 （22）形成在插入件（20）的上表面上。 半导体芯片（30）安装在封装基板（10）的顶面上，插入件（60）粘接到芯片（30）的上部，并且在端子（22）和 端子（11'）。 当以这种方式配置具有组合成一个封装的多个半导体芯片的半导体器件时，可以容易地保证每个半导体芯片的KGD（Known-Good-Die），并且可以以高产量的良好单元制造半导体器件。 此外，半导体芯片可以原样使用，而不限制其端子的位置，间距，信号布置等。
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公开(公告)号：US07723835B2
公开(公告)日：2010-05-25
申请号：US12235734
申请日：2008-09-23
IPC分类号： H01L23/02
CPC分类号： H01L23/3135 , H01L23/3128 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2225/0651 , H01L2225/06513 , H01L2225/0652 , H01L2225/06572 , H01L2225/06582 , H01L2225/06596 , H01L2924/00014 , H01L2924/01004 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11′). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.
摘要翻译： 半导体芯片安装插入件（60）通过在半导体芯片（50）和插入件（20）之间执行引线键合而构成，其中连接到芯片（50）的端子（51）的端子（21）和分离的端子 （22）形成在插入件（20）的上表面上。 半导体芯片（30）安装在封装基板（10）的顶面上，插入件（60）粘接到芯片（30）的上部，并且在端子（22）和 端子（11'）。 当以这种方式配置具有组合成一个封装的多个半导体芯片的半导体器件时，可以容易地保证每个半导体芯片的KGD（Known-Good-Die），并且可以以高产量的良好单元制造半导体器件。 此外，半导体芯片可以原样使用，而不限制其端子的位置，间距，信号布置等。
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8.发明申请Semiconductor chip mounted interposer, semiconductor device, semiconductor chip interposer fabrication method, bare chip mounted interposer, and interposer sheet 审中-公开半导体芯片安装的内插器，半导体器件，半导体芯片插入器制造方法，裸芯片安装的插入器和插入片公开(公告)号：US20070132080A1
公开(公告)日：2007-06-14
申请号：US10595424
申请日：2003-12-15
IPC分类号： H01L23/02
CPC分类号： H01L23/3135 , H01L23/3128 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2225/0651 , H01L2225/06513 , H01L2225/0652 , H01L2225/06572 , H01L2225/06582 , H01L2225/06596 , H01L2924/00014 , H01L2924/01004 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11′). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.
摘要翻译： 半导体芯片安装插入件（60）通过在半导体芯片（50）和插入件（20）之间执行引线键合而构成，其中连接到芯片（50）的端子（51）的端子（21）和分离的端子 （22）形成在插入件（20）的上表面上。 半导体芯片（30）安装在封装基板（10）的顶面上，插入件（60）粘接到芯片（30）的上部，并且在端子（22）和 端子（11'）。 当以这种方式配置具有组合成一个封装的多个半导体芯片的半导体器件时，可以容易地保证每个半导体芯片的KGD（Known-Good-Die），并且可以以高产量的良好单元制造半导体器件。 此外，半导体芯片可以原样使用，而不限制其端子的位置，间距，信号布置等。
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公开(公告)号：US20120014181A1
公开(公告)日：2012-01-19
申请号：US13205900
申请日：2011-08-09
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。
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公开(公告)号：US07573742B2
公开(公告)日：2009-08-11
申请号：US11550335
申请日：2006-10-17
IPC分类号： G11C16/04
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/12 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11568
摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and bit data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.
摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行位数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。
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