公开(公告)号：US08044498B2

公开(公告)日：2011-10-25

申请号：US12164503

申请日：2008-06-30

申请人： Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

发明人： Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC分类号： H01L23/07

CPC分类号： H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012

摘要： A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on.Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.

摘要翻译： 可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。 使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。 提供给半导体芯片安装的密封子板的突起附接到封装基板。 多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。

公开(公告)号：US20090175083A1

公开(公告)日：2009-07-09

申请号：US11684035

申请日：2007-03-09

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3436

摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

摘要翻译： 非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US06867455B2

公开(公告)日：2005-03-15

申请号：US10600344

申请日：2003-06-23

申请人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

发明人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/26586 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7923

摘要： A semiconductor device capable of holding multibit information in one memory cell, and a method of manufacturing the semiconductor device. A trench is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film of a gate insulating film which interpose the trench are caused to function as first and second electric charge holding portions capable of holding electric charges. In the case in which first electric charges are trapped on the drain side and second electric charges are trapped on the source side, a portion of a gate electrode in the trench functions as a shield. If a fixed potential is given to the gate electrode, the second electric charge holding portion is not influenced by an electric field induced by the first electric charges so that the trapping of the second electric charges is not inhibited.

摘要翻译： 一种能够将多位信息保持在一个存储单元中的半导体器件，以及半导体器件的制造方法。 在MONOS晶体管的沟道部分中形成沟槽。 然后，使介入沟槽的栅极绝缘膜的氮化硅膜中的源极侧部分和漏极侧部分作为能够保持电荷的第一和第二电荷保持部分起作用。 在第一电荷被捕获在漏极侧并且第二电荷被捕获在源极侧的情况下，沟槽中的栅电极的一部分用作屏蔽。 如果向栅电极施加固定电位，则第二电荷保持部不受第一电荷引起的电场的影响，从而不抑制第二电荷的捕获。

公开(公告)号：US06441426B1

公开(公告)日：2002-08-27

申请号：US09333687

申请日：1999-06-16

申请人： Atsushi Fukumoto ,  Natsuo Ajika

发明人： Atsushi Fukumoto ,  Natsuo Ajika

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7883 ,  Y10S257/90

摘要： In a semiconductor substrate surface, first and second trenches extending in parallel with each other in a bit line direction are provided. An insulation film for trench isolation is filled in the first and second trenches. A floating gate is provided between the first and second trenches on the semiconductor substrate. A sidewall spacer is provided on a sidewall surface, extending in the bit line direction, of the floating gate.

摘要翻译： 在半导体衬底表面中，提供沿位线方向彼此平行延伸的第一和第二沟槽。 用于沟槽隔离的绝缘膜填充在第一和第二沟槽中。 浮置栅极设置在半导体衬底上的第一和第二沟槽之间。 侧壁间隔件设置在浮动栅极的位线方向上延伸的侧壁表面上。

公开(公告)号：US6014328A

公开(公告)日：2000-01-11

申请号：US35786

申请日：1998-03-06

申请人： Takahiro Onakado ,  Natsuo Ajika

发明人： Takahiro Onakado ,  Natsuo Ajika

IPC分类号： G11C16/04 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  G11C16/0433 ,  H01L27/115

摘要： In a nonvolatile semiconductor memory device, a memory cell array includes memory cell transistors and cell select transistors corresponding to the memory cell transistors, respectively. A memory cell SG decoder supplies a potential to a cell select line corresponding to the selected row. The cell select transistor opens and closes a conduction path of a current flowing between a bit line and a source line through the memory cell transistor in accordance with the potential on the cell select line. As a result, an influence by a leak current flowing from the unselected memory cell transistor in a read operation is suppressed.

摘要翻译： 在非易失性半导体存储器件中，存储单元阵列分别包括与存储单元晶体管对应的存储单元晶体管和单元选择晶体管。 存储单元SG解码器向对应于所选行的单元选择线提供电位。 电池选择晶体管根据电池选择线上的电位来打开和闭合通过存储单元晶体管在位线和源极线之间流动的电流的导通路径。 结果，抑制了在读取操作中从未选择的存储单元晶体管流过的漏电流的影响。

公开(公告)号：US5898606A

公开(公告)日：1999-04-27

申请号：US841372

申请日：1997-04-30

申请人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda ,  Atsushi Fukumoto ,  Makoto Ohi

发明人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda ,  Atsushi Fukumoto ,  Makoto Ohi

IPC分类号： G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00

CPC分类号： H01L27/11517 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/16 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/7883

摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

摘要翻译： 在擦除时，电子同时从多个存储单元的源中注入到浮动栅极中。 因此，多个存储单元的阈值电压增加。 在编程中，电子从所选择的存储单元的浮动栅极发射到漏极。 因此，所选存储单元的阈值电压降低。

公开(公告)号：US5446301A

公开(公告)日：1995-08-29

申请号：US274517

申请日：1994-07-13

申请人： Koji Eguchi ,  Natsuo Ajika ,  Kazuyuki Sugahara

发明人： Koji Eguchi ,  Natsuo Ajika ,  Kazuyuki Sugahara

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/768 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01 ,  H01L29/06

CPC分类号： H01L29/66772 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78654

摘要： A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.

摘要翻译： 公开了能够有效地防止栅极氧化膜的介电击穿而不会不利地影响晶体管的特性的半导体器件及其制造方法。 该半导体器件包括通过溅射蚀刻使上角部分被倒圆的SOI膜2和形成在具有几乎均匀厚度的SOI膜2上的栅极氧化膜3。 因此，SOI膜2的上角部的电场浓度降低。 此外，通过均匀的栅极氧化膜3增强晶体管的控制特性。结果，有效地防止了栅极氧化膜的电介质击穿，而不会不利地影响晶体管的特性。 使用能够在低温下进行的溅射蚀刻，使得SOI膜2的上角部分被倒圆而不会对形成在下层中的半导体元件产生不利影响。

公开(公告)号：US5381365A

公开(公告)日：1995-01-10

申请号：US91675

申请日：1993-06-30

申请人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

发明人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

IPC分类号： H01L27/108 ,  H01L29/68 ,  H01L27/10

CPC分类号： H01L27/10817

摘要： The DRAM according to the present invention comprises so-called cylindrical stacked type capacitors. Each of the cylindrical stacked type capacitors comprises a base portion extending flat on an insulation layer and a surface of a substrate, and a cylindrical portion extending vertically and upwardly from the base portion. Then, the cylindrical portion vertically and upwardly protrudes from an outermost peripheral position of the base portion. As a result, an area where electrodes of the capacitor and capacitance of the capacitor can be increased. Furthermore, with a bit line located below an electrode layer of the capacitor, adjacent capacitors above the bit line can be isolated. Accordingly, it is possible to prevent the bit line contact from defining an isolation distance between the capacitors. Furthermore, an isolating layer patterned by etching is used as an isolating region between the capacitors and a lower electrode of the capacitor is formed along a surface of the isolating layer to form an isolation region between the adjacent capacitors. In addition, the lower electrode of the cylindrical stacked type capacitor is integrally formed by using a step formed in the insulation layer. As a result, the manufacturing step is simplified.

摘要翻译： 根据本发明的DRAM包括所谓的圆柱形堆叠型电容器。 每个圆柱形堆叠型电容器包括在绝缘层和基板的表面上平坦延伸的基部，以及从基部垂直和向上延伸的圆柱形部分。 然后，圆筒部从基部的最外周位置向上方突出。 结果，可以增加电容器的电极和电容器的电容的区域。 此外，通过位于电容器的电极层下方的位线，可以隔离位线上方的相邻电容器。 因此，可以防止位线接触限定电容器之间的隔离距离。 此外，通过蚀刻图案化的隔离层用作电容器之间的隔离区域，并且电容器的下电极沿着隔离层的表面形成，以在相邻的电容器之间形成隔离区域。 此外，圆柱形堆叠型电容器的下电极通过使用形成在绝缘层中的台阶整体地形成。 结果，简化了制造步骤。

公开(公告)号：US5381029A

公开(公告)日：1995-01-10

申请号：US838993

申请日：1992-02-21

申请人： Koji Eguchi ,  Natsuo Ajika ,  Kazuyuki Sugahara

发明人： Koji Eguchi ,  Natsuo Ajika ,  Kazuyuki Sugahara

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/768 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01 ,  H01L29/06

CPC分类号： H01L29/66772 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78654

摘要： A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.

公开(公告)号：US5338957A

公开(公告)日：1994-08-16

申请号：US110151

申请日：1993-08-23

申请人： Atsushi Fukumoto ,  Makoto Ohi ,  Hiroshi Onoda ,  Natsuo Ajika ,  Yuichi Kunori

发明人： Atsushi Fukumoto ,  Makoto Ohi ,  Hiroshi Onoda ,  Natsuo Ajika ,  Yuichi Kunori

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/68 ,  G11C11/34

CPC分类号： H01L27/115

摘要： The width of a charge storage electrode and a control electrode in the column direction is set to be wider above an element isolation region than that above a channel region. Therefore, the capacitance between the control electrode and the charge storage electrode can be increased to improve the coupling ratio in a nonvolatile semiconductor memory device. Also, a first interconnection layer is equal in height above the control electrode and above the channel region, so that patterning of the first interconnection layer can be carried out easily and precisely.

摘要翻译： 在列方向上的电荷存储电极和控制电极的宽度被设定为比元件隔离区域高于沟道区域以上的宽度。 因此，可以增加控制电极和电荷存储电极之间的电容，以提高非易失性半导体存储器件中的耦合比。 此外，第一互连层在控制电极上方高于沟道区域的高度相等，使得可以容易且精确地执行第一互连层的图案化。