Semiconductor memory comprising dual charge storage nodes and methods for its fabrication

Invention Grant

US07767517B2 Semiconductor memory comprising dual charge storage nodes and methods for its fabrication 有权

Title translation: 半导体存储器包括双电荷存储节点及其制造方法

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Patent Title: Semiconductor memory comprising dual charge storage nodes and methods for its fabrication
Patent Title (中): 半导体存储器包括双电荷存储节点及其制造方法
Application No.: US11613513

Application Date: 2006-12-20
Publication No.: US07767517B2

Publication Date: 2010-08-03
Inventor: Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
Applicant: Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
Applicant Address: US CA Sunnyvale
Assignee: Spansion LLC
Current Assignee: Spansion LLC
Current Assignee Address: US CA Sunnyvale
Main IPC: H01L21/8242
IPC: H01L21/8242

Semiconductor memory comprising dual charge storage nodes and methods for its fabrication

Abstract:

A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

Abstract(Chinese):

提供了双电荷存储节点存储器件及其制造方法。在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。在第二部分上形成一层半导体材料。第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层和第二电介质层。将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

Public/Granted literature

US20080149999A1 SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION Public/Granted day:2008-06-26

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8239	........存储器结构
H01L21/8242	.........动态随机存取存储结构（DRAM）