Invention Grant
US07767575B2 Forming robust solder interconnect structures by reducing effects of seed layer underetching
有权
通过减少种子层脱落的影响，形成坚固的焊料互连结构
- Patent Title: Forming robust solder interconnect structures by reducing effects of seed layer underetching
- Patent Title (中): 通过减少种子层脱落的影响，形成坚固的焊料互连结构
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Application No.: US12348143Application Date: 2009-01-02
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Publication No.: US07767575B2Publication Date: 2010-08-03
- Inventor: Kamalesh K. Srivastava , Subhash L. Shinde , Tien-Jen Cheng , Sarah H. Knickerbocker , Roger A. Quinn , William E. Sablinski , Julie C. Biggs , David E. Eichstadt , Jonathan H. Griffith
- Applicant: Kamalesh K. Srivastava , Subhash L. Shinde , Tien-Jen Cheng , Sarah H. Knickerbocker , Roger A. Quinn , William E. Sablinski , Julie C. Biggs , David E. Eichstadt , Jonathan H. Griffith
- Applicant Address: US CA San Jose
- Assignee: Tessera Intellectual Properties, Inc.
- Current Assignee: Tessera Intellectual Properties, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/48
Abstract:
A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.
Public/Granted literature
- US20090163019A1 FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING Public/Granted day:2009-06-25
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