发明授权
US07768287B2 Methods and apparatus for managing defective processors through power gating
有权
通过电源门控管理有缺陷的处理器的方法和设备
- 专利标题： Methods and apparatus for managing defective processors through power gating
- 专利标题（中）： 通过电源门控管理有缺陷的处理器的方法和设备
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申请号： US11620873申请日： 2007-01-08
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公开(公告)号： US07768287B2公开(公告)日： 2010-08-03
- 发明人: Atsushi Hayashi , Akiyuki Hatakeyama , Taichi Niki , Yoichi Nishino
- 申请人： Atsushi Hayashi , Akiyuki Hatakeyama , Taichi Niki , Yoichi Nishino
- 申请人地址： JP Tokyo
- 专利权人： Sony Computer Enterainment Inc.
- 当前专利权人： Sony Computer Enterainment Inc.
- 当前专利权人地址： JP Tokyo
- 代理机构： Gibson & Dernier LLP
- 代理商 Matthew B. Dernier, Esq.
- 主分类号： G01R31/02
- IPC分类号： G01R31/02 ; G06F1/26
摘要：
Methods and apparatus provide for: selectively supplying a first source of power to a plurality of circuit blocks of a system using a plurality of gate circuits responsive to respective control signals provided by at least one control circuit; and providing a second source of power to operate the control circuit before the first source of power is available to the gate circuits such that the control signals are valid before such availability.
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