Invention Grant
- Patent Title: Resistive memory structure with buffer layer
- Patent Title (中): 具有缓冲层的电阻式存储器结构
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Application No.: US12176183Application Date: 2008-07-18
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Publication No.: US07777215B2Publication Date: 2010-08-17
- Inventor: Wei-Chih Chien , Kuo-Pin Chang , Erh-Kun Lai , Kuang Yeu Hsieh
- Applicant: Wei-Chih Chien , Kuo-Pin Chang , Erh-Kun Lai , Kuang Yeu Hsieh
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Agent James F. Hann
- Main IPC: H01L47/00
- IPC: H01L47/00

Abstract:
A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.
Public/Granted literature
- US20090020740A1 RESISTIVE MEMORY STRUCTURE WITH BUFFER LAYER Public/Granted day:2009-01-22
Information query
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