公开(公告)号：US20140054535A1

公开(公告)日：2014-02-27

申请号：US13594353

申请日：2012-08-24

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

IPC分类号： H01L47/00

CPC分类号： H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

摘要翻译： 具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。

公开(公告)号：US20130277799A1

公开(公告)日：2013-10-24

申请号：US13451428

申请日：2012-04-19

申请人： Shih-Hung Chen ,  Kuang-Yeu Hsieh

发明人： Shih-Hung Chen ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/91

摘要： An example of a capacitor includes a series of ridges and trenches and an interconnect region on the integrated circuit substrate. The series of ridges and trenches and the interconnect region have a capacitor foundation surface with a serpentine cross-sectional shape on the series of ridges and trenches. Electrical conductors are electrically connected to the electrode layers from the interconnect region for access to the electrode layers of the capacitor assembly.

摘要翻译： 电容器的示例包括集成电路基板上的一系列脊和沟槽和互连区域。 一系列脊和沟槽和互连区域具有在一系列脊和沟槽上具有蛇形横截面形状的电容器基座表面。 电导体从互连区域电连接到电极层，用于进入电容器组件的电极层。

公开(公告)号：US08362615B2

公开(公告)日：2013-01-29

申请号：US11892980

申请日：2007-08-29

申请人： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578

摘要： A memory and a manufacturing method thereof are provided. The memory includes a dielectric layer, a polysilicon layer, a first buried diffusion, a second buried diffusion, a charge storage structure and a gate. The polysilicon layer is disposed on the dielectric layer and electrically connected to at least a voltage. The first buried diffusion and the second buried diffusion are separately disposed in the surface of the polysilicon layer. The charge storage structure is disposed on the polysilicon layer and positioned between the first buried diffusion and the second buried diffusion. The gate is disposed on the charge storage structure.

公开(公告)号：US08243494B2

公开(公告)日：2012-08-14

申请号：US12235773

申请日：2008-09-23

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

IPC分类号： G11C16/02 ,  H01L29/417

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

摘要翻译： 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

公开(公告)号：US08178405B2

公开(公告)日：2012-05-15

申请号：US12755897

申请日：2010-04-07

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/8242

CPC分类号： H01L45/122 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1683

摘要： A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.

摘要翻译： 存储单元装置具有底部电极和顶部电极，与底部电极接触的存储器材料的插头以及具有接触顶部电极的边缘和接触存储器的底部开口的杯形导电构件 材料。 因此，存储单元中的导电路径从顶部电极通过导电杯状构件，并通过相变材料的塞子到达底部电极。 此外，用于制造存储单元器件的方法包括在底部电极上形成包括绝缘元件和止动元件的底部电极岛的步骤，形成围绕岛的分离层，去除止动元件以在绝缘元件上方形成孔 在分离层中，在孔中形成导电膜，在导电膜上形成绝缘衬垫，进行蚀刻以形成具有边缘的杯形导电膜，并且通过绝缘衬垫和杯状导电体的底部形成开口 在底部电极的表面形成薄膜，在开口中形成相变记忆材料塞，形成与杯状导电膜的边缘接触的顶部电极。

公开(公告)号：US20120108031A1

公开(公告)日：2012-05-03

申请号：US13346935

申请日：2012-01-10

申请人： Ming-Daou LEE ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou LEE ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/02

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

摘要翻译： 提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。 绝缘层设置在底部电极上。 绝缘层具有第一宽度的接触孔。 硬掩模层具有开口。 存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。 顶部电极设置在绝缘层上并与存储单元耦合。

公开(公告)号：US08139393B2

公开(公告)日：2012-03-20

申请号：US12576212

申请日：2009-10-08

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/122 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1633

摘要： A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer.

摘要翻译： 可选择地显示第一和第二逻辑电平的存储器件。 第一导电材料具有形成在其上的第一存储层的第一表面，并且第二导电材料具有形成在其上的第二存储层的第二表面。 连接导电层连接第一和第二存储层并将其放置在电接触中。 该结构被设计成使得第一存储层的横截面积小于第二存储层的横截面面积。

公开(公告)号：US07977735B2

公开(公告)日：2011-07-12

申请号：US12717076

申请日：2010-03-03

申请人： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/792

摘要： A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.

摘要翻译： 堆叠的非易失性存储器件包括堆叠在彼此顶部的多个位线和字线层。 位线层包括多个位线，其可以使用先进的处理技术形成，从而使器件的制造成本高效且成本有效。 该器件可以配置为NAND操作。

公开(公告)号：US07973366B2

公开(公告)日：2011-07-05

申请号：US11352788

申请日：2006-02-13

申请人： Chia-Hua Ho ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Chia-Hua Ho ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/792

CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

摘要： Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.

摘要翻译： 存储单元，其包括具有由沟道区域分离的源极区域和漏极区域的半导体衬底; 电荷捕获结构，设置在所述半导体衬底的沟道区之上; 设置在电荷捕获结构上方并靠近源极区的第一栅极; 以及第二栅极，其设置在所述电荷捕获结构的上方并且靠近所述漏极区; 提供了第一栅极和第二栅极被第一纳米级分隔开的区域，以及包括多个这样的电池的阵列，制造这种电池的方法以及操作这种电池的方法。

公开(公告)号：US07972893B2

公开(公告)日：2011-07-05

申请号：US12469184

申请日：2009-05-20

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/00

CPC分类号： H01L45/1226 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes.

摘要翻译： 制造存储器件的方法包括提供具有第一和第二向上和向内渐缩的表面的电介质材料以及连接第一和第二表面的表面段。 第一和第二电极形成在第一和第二表面上。 存储元件形成在表面段上以电连接第一和第二电极。