中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

24 records (took 0.019 seconds)

    Resistive Memory Structure with Buffer Layer
    1.
    发明申请
    Resistive Memory Structure with Buffer Layer 审中-公开
    具有缓冲层的电阻式存储器结构

    公开(公告)号：US20110189819A1

    公开(公告)日：2011-08-04

    申请号：US13083450

    申请日：2011-04-08

    Applicant: Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    Inventor： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC: H01L21/8239

    CPC classification number: H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633 ,  Y10S438/90

    Abstract: A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

    Abstract translation: 存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。 记忆元件包括一种或多种金属氧化合物。 缓冲层包括氧化物和氮化物中的至少一种。 另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。 记忆体包括一种或多种金属氧化合物。 制造存储器件的方法的一个例子包括形成第一和第二电极。 形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

    Resistive memory structure with buffer layer
    2.
    发明授权
    Resistive memory structure with buffer layer 有权
    具有缓冲层的电阻式存储器结构

    公开(公告)号：US07943920B2

    公开(公告)日：2011-05-17

    申请号：US12836304

    申请日：2010-07-14

    Applicant: Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    Inventor： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC: H01L29/04

    CPC classification number: H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633 ,  Y10S438/90

    Abstract: A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

    Abstract translation: 存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。 记忆元件包括一种或多种金属氧化合物。 缓冲层包括氧化物和氮化物中的至少一种。 另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。 记忆体包括一种或多种金属氧化合物。 制造存储器件的方法的一个例子包括形成第一和第二电极。 形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

    Resistive memory structure with buffer layer
    3.
    发明授权
    Resistive memory structure with buffer layer 有权
    具有缓冲层的电阻式存储器结构

    公开(公告)号：US07777215B2

    公开(公告)日：2010-08-17

    申请号：US12176183

    申请日：2008-07-18

    Applicant: Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    Inventor： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC: H01L47/00

    CPC classification number: H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633 ,  Y10S438/90

    Abstract: A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

    Abstract translation: 存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。 记忆元件包括一种或多种金属氧化合物。 缓冲层包括氧化物和氮化物中的至少一种。 另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。 记忆体包括一种或多种金属氧化合物。 制造存储器件的方法的一个例子包括形成第一和第二电极。 形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

    RESISTIVE MEMORY STRUCTURE WITH BUFFER LAYER
    5.
    发明申请
    RESISTIVE MEMORY STRUCTURE WITH BUFFER LAYER 有权
    电阻记忆结构与缓冲层

    公开(公告)号：US20090020740A1

    公开(公告)日：2009-01-22

    申请号：US12176183

    申请日：2008-07-18

    Applicant: Wei-Chih CHIEN ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    Inventor： Wei-Chih CHIEN ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC: H01L47/00 ,  H01L21/00

    CPC classification number: H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633 ,  Y10S438/90

    Abstract: A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

    Abstract translation: 存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。 记忆元件包括一种或多种金属氧化合物。 缓冲层包括氧化物和氮化物中的至少一种。 另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。 记忆体包括一种或多种金属氧化合物。 制造存储器件的方法的一个例子包括形成第一和第二电极。 形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

    Resistive memory device and manufacturing method thereof and operating method thereof
    6.
    发明授权
    Resistive memory device and manufacturing method thereof and operating method thereof 有权
    电阻式存储器件及其制造方法及其操作方法

    公开(公告)号：US08501574B2

    公开(公告)日：2013-08-06

    申请号：US12574938

    申请日：2009-10-07

    Applicant: Kuo-Pin Chang ,  Hang-Ting Lue ,  Cheng-Hung Tsai

    Inventor： Kuo-Pin Chang ,  Hang-Ting Lue ,  Cheng-Hung Tsai

    IPC: H01L21/20

    CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/0011 ,  H01L27/24 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16

    Abstract: A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers electrically coupled to the third impurity diffusion layers; and forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers.

    Abstract translation: 制造电阻式存储器的方法包括以下步骤：在衬底中形成具有第一杂质扩散层，第二杂质扩散层和第三杂质扩散层的第一注入层叠结构; 蚀刻至少所述第一注入层叠结构以形成多个第二注入层叠结构，其中所述第一杂质扩散层为第一信号线; 在所述第二植入层叠结构之间形成多个第一绝缘层; 蚀刻所述第二注入层叠结构以形成多个第三注入层叠结构，其中所述第一信号线未被蚀刻; 在所述第三植入层叠结构之间形成多个第二绝缘层; 形成电耦合到所述第三杂质扩散层的多个存储材料层; 以及形成垂直于第一信号线的多个第二信号线，并电耦合到存储材料层。

    TRANSISTOR HAVING AN ADJUSTABLE GATE RESISTANCE AND SEMICONDUCTOR DEVICE COMPRISING THE SAME
    9.
    发明申请
    TRANSISTOR HAVING AN ADJUSTABLE GATE RESISTANCE AND SEMICONDUCTOR DEVICE COMPRISING THE SAME 有权
    具有可调节栅极电阻的晶体管和包含该栅极电阻的半导体器件

    公开(公告)号：US20120020138A1

    公开(公告)日：2012-01-26

    申请号：US12839842

    申请日：2010-07-20

    Applicant: Hang-Ting Lue ,  Kuo-Pin Chang

    Inventor： Hang-Ting Lue ,  Kuo-Pin Chang

    IPC: G11C5/06

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C11/5692 ,  G11C16/0483 ,  G11C17/165 ,  G11C2013/0071 ,  G11C2213/15 ,  G11C2213/53 ,  G11C2213/75

    Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.

    Abstract translation: 存储器件包括每个能够存储多个数据位的存储器单元的阵列。 存储单元被布置在连接到公共源极线的存储器串中。 每个存储单元包括与电阻串联连接的可编程晶体管。 晶体管包括可在多个不同电阻值之间切换的栅极电介质。 晶体管的阈值电压根据栅极电介质的电阻值而变化。 因此，存储器单元的存储器状态可以与晶体管的电介质层的相应电阻值相关联。

Patent Agency Ranking