发明授权
US07782853B2 Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine
有权
使用完全可配置存储器,多级流水线逻辑和嵌入式处理器来实现多位特里算法网络搜索引擎的装置和方法
- 专利标题: Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine
- 专利标题(中): 使用完全可配置存储器,多级流水线逻辑和嵌入式处理器来实现多位特里算法网络搜索引擎的装置和方法
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申请号: US10313174申请日: 2002-12-06
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公开(公告)号: US07782853B2公开(公告)日: 2010-08-24
- 发明人: Lun Bin Huang , Suresh Rajgopal , Nicholas Julian Richardson
- 申请人: Lun Bin Huang , Suresh Rajgopal , Nicholas Julian Richardson
- 申请人地址: US TX Carrollton
- 专利权人: STMicroelectronics, Inc.
- 当前专利权人: STMicroelectronics, Inc.
- 当前专利权人地址: US TX Carrollton
- 代理商 Lisa K. Jorgenson; William A. Munck
- 主分类号: H04L12/28
- IPC分类号: H04L12/28 ; G06F7/00 ; G06F9/26
摘要:
A multi-bit trie network search engine is implemented by a number of pipeline logic units corresponding to the number of longest-prefix strides and a set of memory blocks for holding prefix tables. Each pipeline logic unit is limited to one memory access, and the termination point within the pipeline logic unit chain is variable to handle different length prefixes. The memory blocks are coupled to the pipeline logic units with a meshed crossbar and form a set of virtual memory banks, where memory blocks within any given physical memory bank may be allocated to a virtual memory bank for any particular pipeline logic unit. An embedded programmable processor manages route insertion and deletion in the prefix tables, together with configuration of the virtual memory banks.
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