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1.发明授权Mechanism to reduce lookup latency in a pipelined hardware implementation of a trie-based IP lookup algorithm 有权减少基于Trie的IP查找算法的流水线硬件实现中的查找延迟的机制公开(公告)号：US07924839B2
公开(公告)日：2011-04-12
申请号：US10313395
申请日：2002-12-06
IPC分类号： H04L12/28
CPC分类号： G06F17/30985
摘要： A series of hardware pipeline units each processing a stride during prefix search operations on a multi-bit trie includes, within at least one pipeline unit other than the last pipeline unit, a mechanism for retiring search results from the respective pipeline unit rather than passing the search results through the remaining pipeline units. Early retirement may be triggered by either the absence of subsequent strides to be processed or completion (a miss or end node match) of the search, together with an absence of active search operations in subsequent pipeline units. The early retirement mechanism may be included in those pipeline units corresponding to a last stride for a maximum prefix length shorter than the pipeline (e.g., 20 or 32 bits rather than 64 bits), in pipeline units selected on some other basis, or in every pipeline unit. Worst-case and/or average latency for prefix search operations is reduced.
摘要翻译： 在多位特务的前缀搜索操作期间，每个处理步幅的一系列硬件流水线单元包括在除了最后一个流水线单元之外的至少一个流水线单元内，用于从相应流水线单元退出搜索结果的机制， 搜索结果通过剩余的管道单位。 提前退休可能是由于缺少要处理或完成的后续步骤（遗漏或结束节点匹配）的搜索，以及后续流水线单元中没有主动搜索操作可能触发。 早期退休机制可以被包括在对应于最后一步的流水线单元中，其最大前缀长度短于流水线（例如，20位或32位，而不是64位），以某种其他方式选择的流水线单元 管道单元。 前缀搜索操作的最差情况和/或平均延迟减少。
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2.发明授权Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine 有权使用完全可配置存储器，多级流水线逻辑和嵌入式处理器来实现多位特里算法网络搜索引擎的装置和方法公开(公告)号：US07782853B2
公开(公告)日：2010-08-24
申请号：US10313174
申请日：2002-12-06
CPC分类号： H04L45/54
摘要： A multi-bit trie network search engine is implemented by a number of pipeline logic units corresponding to the number of longest-prefix strides and a set of memory blocks for holding prefix tables. Each pipeline logic unit is limited to one memory access, and the termination point within the pipeline logic unit chain is variable to handle different length prefixes. The memory blocks are coupled to the pipeline logic units with a meshed crossbar and form a set of virtual memory banks, where memory blocks within any given physical memory bank may be allocated to a virtual memory bank for any particular pipeline logic unit. An embedded programmable processor manages route insertion and deletion in the prefix tables, together with configuration of the virtual memory banks.
摘要翻译： 多位特里网络搜索引擎由对应于最长前缀步长的数量的流水线逻辑单元和用于保存前缀表的一组存储器块来实现。 每个流水线逻辑单元限于一个存储器访问，并且流水线逻辑单元链中的终止点是可变的，以处理不同长度的前缀。 存储器块通过网格交叉开关连接到流水线逻辑单元并形成一组虚拟存储器组，其中任何给定的物理存储器组中的存储器块可被分配给任何特定流水线逻辑单元的虚拟存储体。 嵌入式可编程处理器管理前缀表中的路由插入和删除以及虚拟存储体的配置。
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3.发明授权System and method for path compression optimization in a pipelined hardware bitmapped multi-bit trie algorithmic network search engine 有权用于流水线硬件位图多位特里计算网络搜索引擎中的路径压缩优化的系统和方法公开(公告)号：US07715392B2
公开(公告)日：2010-05-11
申请号：US10317338
申请日：2002-12-12
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L45/54 , H04L45/7457
摘要： For use in a pipeline network search engine of a router, a path compression optimization system and method is disclosed for eliminating single entry trie tables. The system embeds in a parent trie table (1) path compression patterns that comprise common prefix bits of a data packet and (2) skip counts that indicate the length of the path compression patterns. The network search engine utilizes the path compression patterns and the skip counts to eliminate single entry trie tables from a data structure. Each path compression pattern is processed one stride at a time in subsequent pipeline stages of the network search engine. The elimination of unnecessary single entry trie tables reduces memory space, power consumption, and the number of memory accesses that are necessary to traverse the data structure.
摘要翻译： 为了在路由器的流水线网络搜索引擎中使用，公开了用于消除单进入特技表的路径压缩优化系统和方法。 系统嵌入到父特技表（1）中包含数据包的公共前缀位的路径压缩模式，（2）跳过指示路径压缩模式长度的计数。 网络搜索引擎利用路径压缩模式和跳过计数来消除数据结构中的单条目特征表。 每个路径压缩模式在网络搜索引擎的后续流水线阶段中一次处理一步。 消除不必要的单进入trie表减少了内存空间，功耗以及遍历数据结构所需的内存访问次数。
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4.发明授权Apparatus and method using hashing for efficiently implementing an IP lookup solution in hardware 有权使用散列的设备和方法，用于在硬件中有效地实现IP查找解决方案公开(公告)号：US08295286B2
公开(公告)日：2012-10-23
申请号：US10750012
申请日：2003-12-31
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L45/745 , H04L45/7453 , H04L45/7457 , H04L49/25 , H04L49/55
摘要： Internet Protocol address prefixes are hashed into hash tables allocated memory blocks on demand after collisions occur for both a first hash and a single rehash. The number of memory blocks allocated to each hash table is limited, with additional prefixes handled by an overflow content addressable memory. Each hash table contains only prefixes of a particular length, with different hash tables containing prefixes of different lengths. Only a subset of possible prefix lengths are accommodated by the hash tables, with a remainder of prefixes handled by the content addressable memory or a similar alternate address lookup facility.
摘要翻译： 互联网协议地址前缀被哈希表散列成分配的内存块，按照第一个散列和单个重新发生的冲突发生。 分配给每个散列表的存储器块的数量受限制，其中额外的前缀由溢出内容可寻址存储器处理。 每个散列表仅包含特定长度的前缀，不同的散列表包含不同长度的前缀。 只有哈希表容纳可能的前缀长度的一个子集，其余的前缀由内容可寻址存储器或类似的替代地址查找工具处理。
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5.发明授权Method for increasing storage capacity in a multi-bit trie-based hardware storage engine by compressing the representation of single-length prefixes 有权通过压缩单长度前缀的表示来增加基于多比特特里硬件存储引擎中的存储容量的方法公开(公告)号：US07162481B2
公开(公告)日：2007-01-09
申请号：US10313854
申请日：2002-12-06
CPC分类号： G06F17/30985 , G06F17/30625 , Y10S707/959 , Y10S707/99933 , Y10S707/99934 , Y10S707/99942
摘要： Prefixes terminating with end node entries each containing identical length prefix portions in a single child table are compressed by replacing the end node entries with one or more compressed single length (CSL) prefix entries in the child table that contain a bitmap for the prefix portions for the end node entries. A different type parent table trie node entry is created for the child table. Where the prefix portions are of non-zero length, the parent table contains a bitmap indexing the end node entries. Where the prefix portions are of length zero, the parent table may optionally contain a bitmap for the prefix portions, serving as an end node. The number of prefix portions consolidated within the CSL node entry is based upon the prefix portion length.
摘要翻译： 在单个子表中每个包含相同长度前缀部分的端节点条目终止的前缀通过用子表中的一个或多个压缩单个长度（CSL）前缀条目替换结束节点条目而被压缩，该条目包含前缀部分的位图 结束节点条目。 为子表创建不同类型的父表格特里节点条目。 前缀部分为非零长度的位置，父表包含索引结束节点条目的位图。 在前缀部分的长度为零的情况下，父表可以可选地包含作为结束节点的前缀部分的位图。 在CSL节点条目中合并的前缀部分的数量基于前缀部分长度。
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6.发明授权Method for increasing average storage capacity in a bit-mapped tree-based storage engine by using remappable prefix representations and a run-length encoding scheme that defines multi-length fields to compactly store IP prefixes 有权通过使用可重映射的前缀表示法增加位映射的基于树的存储引擎中的平均存储容量的方法以及定义多长度字段以紧凑地存储IP前缀的游程长度编码方案公开(公告)号：US07099881B2
公开(公告)日：2006-08-29
申请号：US10313416
申请日：2002-12-06
CPC分类号： G06F17/30985 , G06F17/30625 , H04L45/00 , H04L45/54 , H04L45/7457 , Y10S707/922 , Y10S707/99933
摘要： Sparsely distributed prefixes within a bitmapped multi-bit trie are compressed by one or more of: replacing a single entry table string terminating with a single prefix end node with a parent table entry explicitly encoding a prefix portion; replacing a table with only two end nodes or only an end node and an internal node with a single parent table entry explicitly encoding prefix portions; replacing two end nodes with a single compressed child entry at a table location normally occupied by an internal node and explicitly encoding prefix portions; and replacing a plurality of end nodes with a prefix-only entry located at the table end explicitly encoding portions of a plurality of prefixes. The compressed child entry and the prefix-only entry, if present, are read by default each time the table is searched. Run length encoding allows variable length prefix portions to be encoded.
摘要翻译： 位映射的多位特里内的稀疏分布的前缀被以下一个或多个压缩：用单个前缀结束节点替换单个条目表字符串，其中父表项明确地编码前缀部分; 用只有两个端节点或仅一个端节点和一个内部节点替换一个表，其中单个父表项明确地编码前缀部分; 在通常由内部节点占用的表位置处使用单个压缩子条目替换两个端节点，并明确地编码前缀部分; 以及用位于表端的仅前缀条目替换多个端节点，显式地编码多个前缀的部分。 每次搜索表时，默认情况下读取压缩子条目和仅前缀条目（如果存在）。 运行长度编码允许编码可变长度前缀部分。
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7.发明申请Apparatus and method using hashing for efficiently implementing an IP lookup solution in hardware 有权使用散列的设备和方法，用于在硬件中有效地实现IP查找解决方案公开(公告)号：US20050141519A1
公开(公告)日：2005-06-30
申请号：US10750012
申请日：2003-12-31
CPC分类号： H04L45/00 , H04L45/745 , H04L45/7453 , H04L45/7457 , H04L49/25 , H04L49/55
摘要： Internet Protocol address prefixes are hashed into hash tables allocated memory blocks on demand after collisions occur for both a first hash and a single rehash. The number of memory blocks allocated to each hash table is limited, with additional prefixes handled by an overflow content addressable memory. Each hash table contains only prefixes of a particular length, with different hash tables containing prefixes of different lengths. Only a subset of possible prefix lengths are accommodated by the hash tables, with a remainder of prefixes handled by the content addressable memory or a similar alternate address lookup facility.
摘要翻译： 互联网协议地址前缀被哈希表散列成分配的内存块，按照第一个散列和单个重新发生的冲突发生。 分配给每个散列表的存储器块的数量受限制，其中额外的前缀由溢出内容可寻址存储器处理。 每个散列表仅包含特定长度的前缀，不同的散列表包含不同长度的前缀。 只有哈希表容纳可能的前缀长度的一个子集，其余的前缀由内容可寻址存储器或类似的替代地址查找工具处理。
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8.发明授权公开(公告)号：US06363515B1
公开(公告)日：2002-03-26
申请号：US09000588
申请日：1997-12-30
申请人： Suresh Rajgopal , Rakesh J. Patel , Surujeen Singh
发明人： Suresh Rajgopal , Rakesh J. Patel , Surujeen Singh
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A power estimation tool allows the designer to estimate power usage, at the RTL stage for example, of a high performance electronic system design using available information. This enables power estimation before the circuit schematics are created and early enough for power dissipation to be included in the design optimization. The estimation tool, operable at the RTL level, may provide estimates of power usage of functional blocks and the overall system. The tool can take an HDL description of the proposed design and partition that description into a format which can be analyzed for power usage in an automated fashion. The estimated power use can also be modified to account for different circuit design techniques such domino versus static designs and to account for capacitance and layout considerations. In addition, an empirical estimator for clock and data buffer power usage allows these elements to be accounted for before their design is completed. The tool uses a power model library of prior designs to efficiently estimate power dissipation of subsequent designs.
摘要翻译： 功率估计工具允许设计者在使用可用信息的高性能电子系统设计的RTL阶段估计功率使用。 这在电路原理图创建之前实现了功率估计，并且足够早于功耗被包括在设计优化中。 可在RTL级别操作的估计工具可以提供对功能块和整个系统的功率使用的估计。 该工具可以对所提出的设计进行HDL描述，并将该描述分割成可以以自动方式分析功率使用的格式。 估计的功率使用也可以被修改以考虑不同的电路设计技术，例如多米诺骨牌与静态设计，并考虑到电容和布局考虑。 此外，用于时钟和数据缓冲器功率使用的经验估计器允许在设计完成之前对这些元件进行考虑。 该工具使用先前设计的功率模型库来有效估计后续设计的功耗。
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