公开(公告)号：US08644099B2

公开(公告)日：2014-02-04

申请号：US13179466

申请日：2011-07-08

Applicant: Aldo G. Cometti ,  Lun Bin Huang ,  Ashot Melik-Martirosian

Inventor： Aldo G. Cometti ,  Lun Bin Huang ,  Ashot Melik-Martirosian

IPC: G11C7/00

CPC classification number: G11C16/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10

Abstract: Disclosed is an apparatus and method for determining a dwell time in a non-volatile memory circuit after a shutdown of the memory circuit. A voltage shift is calculated by comparing a first read level voltage required to read a test block stored before the shutdown and a second read level voltage required to read a second test block stored after the shutdown. A shutdown time is determined from a look up table indexed by the voltage shift and a number of program/erase cycles. The dwell time is calculated as a function of the drive temperature, a clock, and a block time stamp. Once the dwell time is calculated, a controller calculates a new read level voltage based, in part, on the dwell time and provides one or more programming commands representative of the new read level voltage to the memory circuit to read the memory circuit.

Abstract translation: 公开了一种用于在存储器电路关闭之后确定非易失性存储器电路中的驻留时间的装置和方法。 通过比较读取在关闭之前存储的测试块所需的第一读取电平电压和读取关闭后存储的第二测试块所需的第二读取电平电平来计算电压偏移。 从由电压偏移索引的查找表和编程/擦除周期数确定停机时间。 停留时间是根据驱动器温度，时钟和块时间戳计算的。 一旦计算了停留时间，控制器就部分地基于驻留时间计算新的读取电平电压，并且向存储器电路提供表示新的读取电平电压的一个或多个编程命令以读取存储器电路。

公开(公告)号：US20110167322A1

公开(公告)日：2011-07-07

申请号：US12924658

申请日：2010-10-01

Applicant: Sivagnanam Parthasarathy ,  Lun Bin Huang

Inventor： Sivagnanam Parthasarathy ,  Lun Bin Huang

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/23 ,  H03M13/41

CPC classification number: H03M13/4146 ,  H03M13/4107

Abstract: In one embodiment, systems and methods of operating a SOVA system is disclosed that comprises determining the start and stop values for a trellis tree and using the start and stop values to determine the initial states of a plurality of branches within the trellis tree.

Abstract translation: 在一个实施例中，公开了一种操作SOVA系统的系统和方法，其包括确定网格树的开始和停止值，并使用开始和停止值来确定网格树内的多个分支的初始状态。

公开(公告)号：US07496734B1

公开(公告)日：2009-02-24

申请号：US09561241

申请日：2000-04-28

Applicant: Nicholas J. Richardson ,  Lun Bin Huang

Inventor： Nicholas J. Richardson ,  Lun Bin Huang

IPC: G06F9/30

CPC classification number: G06F9/30134 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3863

Abstract: There is disclosed a data processor comprising 1) a register stack comprising a plurality of architectural registers that stores operands required by instructions executed by the data processor; 2) an instruction execution pipeline comprising N processing stages, where each processing stage performs one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; and 3) at least one mapping register associated with at least one of the N processing stages, wherein the at least one mapping register stores mapping data that may be used to determine a physical register associated with an architectural stack register accessed by the pending instruction.

Abstract translation: 公开了一种数据处理器，包括：1）寄存器堆栈，包括多个结构寄存器，其存储由数据处理器执行的指令所需的操作数; 2）包括N个处理阶段的指令执行流水线，其中每个处理阶段执行与由指令执行管线执行的待决指令相关联的多个执行步骤之一; 以及3）与所述N个处理阶段中的至少一个相关联的至少一个映射寄存器，其中所述至少一个映射寄存器存储映射数据，所述映射数据可用于确定与所述待处理指令访问的架构栈寄存器相关联的物理寄存器。

公开(公告)号：US07099881B2

公开(公告)日：2006-08-29

申请号：US10313416

申请日：2002-12-06

Applicant: Nicholas Julian Richardson ,  Suresh Rajgopal ,  Lun Bin Huang

Inventor： Nicholas Julian Richardson ,  Suresh Rajgopal ,  Lun Bin Huang

IPC: G06F12/00 ,  G06F17/30

CPC classification number: G06F17/30985 ,  G06F17/30625 ,  H04L45/00 ,  H04L45/54 ,  H04L45/7457 ,  Y10S707/922 ,  Y10S707/99933

Abstract: Sparsely distributed prefixes within a bitmapped multi-bit trie are compressed by one or more of: replacing a single entry table string terminating with a single prefix end node with a parent table entry explicitly encoding a prefix portion; replacing a table with only two end nodes or only an end node and an internal node with a single parent table entry explicitly encoding prefix portions; replacing two end nodes with a single compressed child entry at a table location normally occupied by an internal node and explicitly encoding prefix portions; and replacing a plurality of end nodes with a prefix-only entry located at the table end explicitly encoding portions of a plurality of prefixes. The compressed child entry and the prefix-only entry, if present, are read by default each time the table is searched. Run length encoding allows variable length prefix portions to be encoded.

Abstract translation: 位映射的多位特里内的稀疏分布的前缀被以下一个或多个压缩：用单个前缀结束节点替换单个条目表字符串，其中父表项明确地编码前缀部分; 用只有两个端节点或仅一个端节点和一个内部节点替换一个表，其中单个父表项明确地编码前缀部分; 在通常由内部节点占用的表位置处使用单个压缩子条目替换两个端节点，并明确地编码前缀部分; 以及用位于表端的仅前缀条目替换多个端节点，显式地编码多个前缀的部分。 每次搜索表时，默认情况下读取压缩子条目和仅前缀条目（如果存在）。 运行长度编码允许编码可变长度前缀部分。

公开(公告)号：US20050141519A1

公开(公告)日：2005-06-30

申请号：US10750012

申请日：2003-12-31

Applicant: Suresh Rajgopal ,  Lun-bin Huang ,  Nicholas Richardson

Inventor： Suresh Rajgopal ,  Lun-bin Huang ,  Nicholas Richardson

IPC: G06F17/30 ,  H04L12/46 ,  H04L12/56 ,  H04L29/06 ,  H04L12/28

CPC classification number: H04L45/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L45/7457 ,  H04L49/25 ,  H04L49/55

Abstract: Internet Protocol address prefixes are hashed into hash tables allocated memory blocks on demand after collisions occur for both a first hash and a single rehash. The number of memory blocks allocated to each hash table is limited, with additional prefixes handled by an overflow content addressable memory. Each hash table contains only prefixes of a particular length, with different hash tables containing prefixes of different lengths. Only a subset of possible prefix lengths are accommodated by the hash tables, with a remainder of prefixes handled by the content addressable memory or a similar alternate address lookup facility.

Abstract translation: 互联网协议地址前缀被哈希表散列成分配的内存块，按照第一个散列和单个重新发生的冲突发生。 分配给每个散列表的存储器块的数量受限制，其中额外的前缀由溢出内容可寻址存储器处理。 每个散列表仅包含特定长度的前缀，不同的散列表包含不同长度的前缀。 只有哈希表容纳可能的前缀长度的一个子集，其余的前缀由内容可寻址存储器或类似的替代地址查找工具处理。

公开(公告)号：US07924839B2

公开(公告)日：2011-04-12

申请号：US10313395

申请日：2002-12-06

Applicant: Suresh Rajgopal ,  Lun Bin Huang ,  Nicholas Julian Richardson

Inventor： Suresh Rajgopal ,  Lun Bin Huang ,  Nicholas Julian Richardson

IPC: H04L12/28

CPC classification number: G06F17/30985

Abstract: A series of hardware pipeline units each processing a stride during prefix search operations on a multi-bit trie includes, within at least one pipeline unit other than the last pipeline unit, a mechanism for retiring search results from the respective pipeline unit rather than passing the search results through the remaining pipeline units. Early retirement may be triggered by either the absence of subsequent strides to be processed or completion (a miss or end node match) of the search, together with an absence of active search operations in subsequent pipeline units. The early retirement mechanism may be included in those pipeline units corresponding to a last stride for a maximum prefix length shorter than the pipeline (e.g., 20 or 32 bits rather than 64 bits), in pipeline units selected on some other basis, or in every pipeline unit. Worst-case and/or average latency for prefix search operations is reduced.

Abstract translation: 在多位特务的前缀搜索操作期间，每个处理步幅的一系列硬件流水线单元包括在除了最后一个流水线单元之外的至少一个流水线单元内，用于从相应流水线单元退出搜索结果的机制， 搜索结果通过剩余的管道单位。 提前退休可能是由于缺少要处理或完成的后续步骤（遗漏或结束节点匹配）的搜索，以及后续流水线单元中没有主动搜索操作可能触发。 早期退休机制可以被包括在对应于最后一步的流水线单元中，其最大前缀长度短于流水线（例如，20位或32位，而不是64位），以某种其他方式选择的流水线单元 管道单元。 前缀搜索操作的最差情况和/或平均延迟减少。

公开(公告)号：US06694420B2

公开(公告)日：2004-02-17

申请号：US10008726

申请日：2001-12-05

Applicant: Lun Bin Huang

Inventor： Lun Bin Huang

IPC: G06F1206

CPC classification number: G06F9/34 ,  G06F7/026 ,  G06F12/0875 ,  G06F12/0891

Abstract: An address range checking circuit capable of determining if a target address, A[M:0], is within an address space having 2N address locations beginning at a base address location, B[M:0], is disclosed, wherein the address range checking circuit does not require a large comparator circuit. The address range checking circuit comprises: 1) comparison circuitry for determining if the address segment A[N−1:0] is less than the address segment B[N−1:0] and generating on a first control signal; 2) first equivalence detection circuitry for determining if the address segment A[M:N] is equal to the address segment B[M:N] and generating an A=B status signal; 3) second equivalence detection circuitry for determining if the address segment A[M:N] is equal to the address segment B[M:N] plus one and generating an A=B+1 status signal; and 4) a multiplexer that outputs the A=B status signal or the A=B+1 status signal depending on the value of the first control signal.

Abstract translation: 公开了一种地址范围检查电路，其能够确定目标地址A [M：0]是否在从基地址位置B [M：0]开始的具有2个N个地址位置的地址空间内，其中 地址范围检查电路不需要较大的比较器电路。 地址范围检查电路包括：1）用于确定地址段A [N-1：0]是否小于地址段B [N-1：0]并产生第一控制信号的比较电路; 2）用于确定地址段A [M：N]是否等于地址段B [M：N]并产生A = B状态信号的第一等价检测电路; 3）第二等效检测电路，用于确定地址段A [M：N]是否等于地址段B [M：N]加1，并产生A = B + 1状态信号; 以及4）多路复用器，其根据第一控制信号的值输出A = B状态信号或A = B + 1状态信号。

公开(公告)号：US20120239976A1

公开(公告)日：2012-09-20

申请号：US13179466

申请日：2011-07-08

Applicant: Aldo G. COMETTI ,  Lun Bin Huang ,  Ashot Melik-Martirosian

Inventor： Aldo G. COMETTI ,  Lun Bin Huang ,  Ashot Melik-Martirosian

IPC: G06F11/00

CPC classification number: G11C16/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10

Abstract: Disclosed is an apparatus and method for determining a dwell time in a non-volatile memory circuit after a shutdown of the memory circuit. A voltage shift is calculated by comparing a first read level voltage required to read a test block stored before the shutdown and a second read level voltage required to read a second test block stored after the shutdown. A shutdown time is determined from a look up table indexed by the voltage shift and a number of program/erase cycles. The dwell time is calculated as a function of the drive temperature, a clock, and a block time stamp. Once the dwell time is calculated, a controller calculates a new read level voltage based, in part, on the dwell time and provides one or more programming commands representative of the new read level voltage to the memory circuit to read the memory circuit.

Abstract translation: 公开了一种用于在存储器电路关闭之后确定非易失性存储器电路中的驻留时间的装置和方法。 通过比较读取在关闭之前存储的测试块所需的第一读取电平电压和读取关闭后存储的第二测试块所需的第二读取电平电平来计算电压偏移。 从由电压偏移索引的查找表和编程/擦除周期数确定停机时间。 停留时间是根据驱动器温度，时钟和块时间戳计算的。 一旦计算了停留时间，控制器就部分地基于驻留时间计算新的读取电平电压，并且向存储器电路提供表示新的读取电平电压的一个或多个编程命令以读取存储器电路。

公开(公告)号：US07782853B2

公开(公告)日：2010-08-24

申请号：US10313174

申请日：2002-12-06

Applicant: Lun Bin Huang ,  Suresh Rajgopal ,  Nicholas Julian Richardson

Inventor： Lun Bin Huang ,  Suresh Rajgopal ,  Nicholas Julian Richardson

IPC: H04L12/28 ,  G06F7/00 ,  G06F9/26

CPC classification number: H04L45/54

Abstract: A multi-bit trie network search engine is implemented by a number of pipeline logic units corresponding to the number of longest-prefix strides and a set of memory blocks for holding prefix tables. Each pipeline logic unit is limited to one memory access, and the termination point within the pipeline logic unit chain is variable to handle different length prefixes. The memory blocks are coupled to the pipeline logic units with a meshed crossbar and form a set of virtual memory banks, where memory blocks within any given physical memory bank may be allocated to a virtual memory bank for any particular pipeline logic unit. An embedded programmable processor manages route insertion and deletion in the prefix tables, together with configuration of the virtual memory banks.

Abstract translation: 多位特里网络搜索引擎由对应于最长前缀步长的数量的流水线逻辑单元和用于保存前缀表的一组存储器块来实现。 每个流水线逻辑单元限于一个存储器访问，并且流水线逻辑单元链中的终止点是可变的，以处理不同长度的前缀。 存储器块通过网格交叉开关连接到流水线逻辑单元并形成一组虚拟存储器组，其中任何给定的物理存储器组中的存储器块可被分配给任何特定流水线逻辑单元的虚拟存储体。 嵌入式可编程处理器管理前缀表中的路由插入和删除以及虚拟存储体的配置。

公开(公告)号：US07715392B2

公开(公告)日：2010-05-11

申请号：US10317338

申请日：2002-12-12

Applicant: Lun Bin Huang ,  Nicholas Julian Richardson ,  Suresh Rajgopal

Inventor： Lun Bin Huang ,  Nicholas Julian Richardson ,  Suresh Rajgopal

IPC: H04L12/56

CPC classification number: H04L45/00 ,  H04L45/54 ,  H04L45/7457

Abstract: For use in a pipeline network search engine of a router, a path compression optimization system and method is disclosed for eliminating single entry trie tables. The system embeds in a parent trie table (1) path compression patterns that comprise common prefix bits of a data packet and (2) skip counts that indicate the length of the path compression patterns. The network search engine utilizes the path compression patterns and the skip counts to eliminate single entry trie tables from a data structure. Each path compression pattern is processed one stride at a time in subsequent pipeline stages of the network search engine. The elimination of unnecessary single entry trie tables reduces memory space, power consumption, and the number of memory accesses that are necessary to traverse the data structure.

Abstract translation: 为了在路由器的流水线网络搜索引擎中使用，公开了用于消除单进入特技表的路径压缩优化系统和方法。 系统嵌入到父特技表（1）中包含数据包的公共前缀位的路径压缩模式，（2）跳过指示路径压缩模式长度的计数。 网络搜索引擎利用路径压缩模式和跳过计数来消除数据结构中的单条目特征表。 每个路径压缩模式在网络搜索引擎的后续流水线阶段中一次处理一步。 消除不必要的单进入trie表减少了内存空间，功耗以及遍历数据结构所需的内存访问次数。