Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Invention Grant

US07785958B2 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode 有权

Title translation: 制造具有高k栅极电介质层和金属栅电极的半导体器件的方法

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Patent Title: Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
Patent Title (中): 制造具有高k栅极电介质层和金属栅电极的半导体器件的方法
Application No.: US12157796

Application Date: 2008-06-12
Publication No.: US07785958B2

Publication Date: 2010-08-31
Inventor: Mark L. Doczy , Justin K. Brask , Jack Kavalieros , Uday Shah , Matthew V. Metz , Suman Datta , Ramune Nagisetty , Robert S. Chau
Applicant: Mark L. Doczy , Justin K. Brask , Jack Kavalieros , Uday Shah , Matthew V. Metz , Suman Datta , Ramune Nagisetty , Robert S. Chau
Applicant Address: US CA Santa Clara
Assignee: Intel Corporation
Current Assignee: Intel Corporation
Current Assignee Address: US CA Santa Clara
Agent Kenneth A. Nelson
Main IPC: H01L21/8242
IPC: H01L21/8242

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Abstract:

A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.

Abstract(Chinese):

描述制造半导体器件的方法。该方法包括在衬底上形成第一电介质层，在第一介电层内形成沟槽，在衬底上形成第二电介质层。第二电介质层具有形成在沟槽中的第一部分和第二部分。在第二电介质层的第一和第二部分上形成具有第一功函数的第一金属层之后，第一金属层的一部分被转换成具有第二功函数的第二金属层。

Public/Granted literature

US20090042405A1 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode Public/Granted day:2009-02-12

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8239	........存储器结构
H01L21/8242	.........动态随机存取存储结构（DRAM）