发明授权
US07871893B2 Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices
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用于非选择性浅沟槽隔离反应离子蚀刻的方法,用于图案化与高性能高度集成逻辑器件兼容的混合取向器件
- 专利标题: Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices
- 专利标题(中): 用于非选择性浅沟槽隔离反应离子蚀刻的方法,用于图案化与高性能高度集成逻辑器件兼容的混合取向器件
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申请号: US12020887申请日: 2008-01-28
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公开(公告)号: US07871893B2公开(公告)日: 2011-01-18
- 发明人: Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
- 申请人: Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Gibb I.P. Law Firm, LLC
- 代理商 Lan D. MacKinnon, Esq.
- 主分类号: H01L21/76
- IPC分类号: H01L21/76 ; H01L21/763
摘要:
Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.
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