公开(公告)号：US20090189242A1

公开(公告)日：2009-07-30

申请号：US12020887

申请日：2008-01-28

申请人： Gregory Costrini ,  David M. Dobuzinsky ,  Thomas S. Kanarsky ,  Munir D. Naeem ,  Christopher D. Sheraw ,  Richard Wise

发明人： Gregory Costrini ,  David M. Dobuzinsky ,  Thomas S. Kanarsky ,  Munir D. Naeem ,  Christopher D. Sheraw ,  Richard Wise

IPC分类号： H01L29/00 ,  H01L21/762

CPC分类号： H01L29/045 ,  H01L21/76224

摘要： Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.

摘要翻译： 公开了混合取向技术（HOT）晶片的实施例以及形成具有改进的浅沟槽隔离（STI）结构的HOT晶片的方法，用于在绝缘体上硅（SOI）区域中图案化器件，具有第一晶体取向 和具有第二结晶取向的体区。 使用非选择性蚀刻工艺形成改进的STI结构，以确保所有STI结构，特别是SOI-体界面处的STI结构各自延伸到半导体衬底并且具有基本均匀的（即，单个 材料）和大致平行于衬底的顶表面的平面（即，无自由）底表面。 可选地，可以使用附加的选择性蚀刻工艺来将STI结构延伸到衬底中的预定深度。

公开(公告)号：US07871893B2

公开(公告)日：2011-01-18

申请号：US12020887

申请日：2008-01-28

申请人： Gregory Costrini ,  David M. Dobuzinsky ,  Thomas S. Kanarsky ,  Munir D. Naeem ,  Christopher D. Sheraw ,  Richard Wise

发明人： Gregory Costrini ,  David M. Dobuzinsky ,  Thomas S. Kanarsky ,  Munir D. Naeem ,  Christopher D. Sheraw ,  Richard Wise

IPC分类号： H01L21/76 ,  H01L21/763

CPC分类号： H01L29/045 ,  H01L21/76224

摘要： Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.

摘要翻译： 公开了混合取向技术（HOT）晶片的实施例以及形成具有改进的浅沟槽隔离（STI）结构的HOT晶片的方法，用于在绝缘体上硅（SOI）区域中图案化器件，具有第一晶体取向 和具有第二结晶取向的体区。 使用非选择性蚀刻工艺形成改进的STI结构，以确保所有STI结构，特别是SOI-体界面处的STI结构各自延伸到半导体衬底并且具有基本均匀的（即，单个 材料）和大致平行于衬底的顶表面的平面（即，无自由）底表面。 可选地，可以使用附加的选择性蚀刻工艺来将STI结构延伸到衬底中的预定深度。

公开(公告)号：US08642475B2

公开(公告)日：2014-02-04

申请号：US12975327

申请日：2010-12-21

申请人： Xiang Hu ,  Helen Wang ,  Arifuzzaman (Arif) Sheikh ,  Habib Hichri ,  Richard Wise

发明人： Xiang Hu ,  Helen Wang ,  Arifuzzaman (Arif) Sheikh ,  Habib Hichri ,  Richard Wise

IPC分类号： H01L21/311

CPC分类号： H01L21/31138 ,  H01L21/32139

摘要： A method of manufacturing an integrated circuit system includes: providing a substrate; forming a polysilicon layer over the substrate; forming an anti-reflective coating layer over the polysilicon layer; etching an anti-reflective coating pattern into the anti-reflective coating layer leaving an anti-reflective coating residue over the polysilicon layer; and etching the anti-reflective coating residue with an etchant gas mixture comprising hydrogen bromide, chlorine, and oxygen to remove the anti-reflective coating residue for mitigating the formation of a polysilicon protrusion.

摘要翻译： 集成电路系统的制造方法包括：提供基板; 在衬底上形成多晶硅层; 在所述多晶硅层上形成抗反射涂层; 将抗反射涂层图案蚀刻到抗反射涂层中，在多晶硅层上留下抗反射涂层残留物; 以及用包括溴化氢，氯和氧的蚀刻剂气体混合物蚀刻抗反射涂层残余物以除去抗反射涂层残余物以减轻多晶硅突起的形成。

公开(公告)号：US08569154B2

公开(公告)日：2013-10-29

申请号：US13422415

申请日：2012-03-16

申请人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

发明人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

IPC分类号： H01L21/425 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76847 ,  H01L21/0337 ,  H01L21/32136 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure.

摘要翻译： 一种方法包括在结构上图案化光致抗蚀剂层以限定开口并暴露牺牲衬底层上的第一平面区域，蚀刻到暴露的第一平面区域以形成具有在结构中的第一深度的空腔， 光致抗蚀剂以增加开口的尺寸以在牺牲衬底层上限定第二平面区域，在牺牲衬底层中形成掺杂部分，以及蚀刻空腔以增加空腔的深度以暴露结构中的第一导体，以及 以增加空腔的一部分的平面面积和深度以暴露结构中的第二导体。

公开(公告)号：US20120190196A1

公开(公告)日：2012-07-26

申请号：US13422445

申请日：2012-03-16

申请人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

发明人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

IPC分类号： H01L21/768

CPC分类号： H01L21/76847 ,  H01L21/0337 ,  H01L21/32136 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure.

摘要翻译： 一种方法包括在结构上图案化光致抗蚀剂层以限定开口并暴露衬底层上的第一平面区域，在第一平面区域中形成衬底层的掺杂部分，去除光致抗蚀剂的一部分以形成限定 在衬底层上的第二平面区域，以及蚀刻形成具有由第一开口限定的第一深度的第一腔体，以暴露结构中的第一接触件，并形成由第二开口限定的第二腔室，以暴露第二接触件 结构。

公开(公告)号：US20110171582A1

公开(公告)日：2011-07-14

申请号：US12687289

申请日：2010-01-14

申请人： Mukta G. Farooq ,  Ramona Kei ,  Emily R. Kinser ,  Anthony D. Lisi ,  Richard Wise ,  Hakeem Yusuff

发明人： Mukta G. Farooq ,  Ramona Kei ,  Emily R. Kinser ,  Anthony D. Lisi ,  Richard Wise ,  Hakeem Yusuff

IPC分类号： G03F7/20

CPC分类号： H01L21/76898 ,  H01L21/3085 ,  H01L25/0657 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed which includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.

摘要翻译： 公开了一种方法，其包括在结构的衬底上图案化光致抗蚀剂层，去除光致抗蚀剂层的第一部分以暴露衬底的第一区域，蚀刻第一区域以形成具有第一深度的空腔， 光致抗蚀剂的一部分以暴露衬底的附加区域，并且蚀刻该腔以暴露结构中的第一导体和附加区域以暴露该结构中的第二导体。

公开(公告)号：US07776695B2

公开(公告)日：2010-08-17

申请号：US11306716

申请日：2006-01-09

申请人： John C. Arnold ,  Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Siddhartha Panda ,  Brian L. Tessier ,  Richard Wise

发明人： John C. Arnold ,  Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Siddhartha Panda ,  Brian L. Tessier ,  Richard Wise

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843

摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.

摘要翻译： 一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域 栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。

公开(公告)号：US07671421B2

公开(公告)日：2010-03-02

申请号：US11444011

申请日：2006-05-31

申请人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/00

CPC分类号： H01L21/28079 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/6659

摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

摘要翻译： 制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。 第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。 平坦化层位于第二栅极材料层上。 平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。 也可以在第一栅极叠层上形成蚀刻停止层。 所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

公开(公告)号：US20090008785A1

公开(公告)日：2009-01-08

申请号：US12027407

申请日：2008-02-07

申请人： Scott D. ALLEN ,  Kenneth A. Bandy ,  Sadanand V. Deshpande ,  Richard Wise

发明人： Scott D. ALLEN ,  Kenneth A. Bandy ,  Sadanand V. Deshpande ,  Richard Wise

IPC分类号： H01L23/48

CPC分类号： H01L21/76802 ,  H01L21/31116

摘要： The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer, at the contact surface. The contact resistance at contact surface is reduced, thereby improving the performance of the device

摘要翻译： 本发明的实施例通常涉及蚀刻工艺，更具体地涉及用于提高硅化镍上的电介质触点的产量的蚀刻处理。 在蚀刻过程中使用无氧原料气，以减少或消除在接触表面处的残余物，包括硅化物层的氧化和消耗。 接触表面的接触电阻降低，从而提高器件的性能

公开(公告)号：US20080093629A1

公开(公告)日：2008-04-24

申请号：US11955591

申请日：2007-12-13

申请人： Huajie Chen ,  Judson Holt ,  Rangarajan Jagannathan ,  Wesley Natzle ,  Michael Sievers ,  Richard Wise

发明人： Huajie Chen ,  Judson Holt ,  Rangarajan Jagannathan ,  Wesley Natzle ,  Michael Sievers ,  Richard Wise

IPC分类号： H01L29/778

CPC分类号： H01L29/66636 ,  H01L29/6659 ,  H01L29/7833

摘要： Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.

摘要翻译： 公开了具有限定的限定的卤素的MOSFET的实施例，其限定的源极/漏极扩展部分以及形成MOSFET的方法。 蚀刻半导体层以形成切割栅极介电层的凹部。 低能量植入物形成晕轮。 然后，执行COR预清洁，并且通过外延沉积填充凹部。 外延可以被原位掺杂或随后植入以形成源/漏扩展。 或者，蚀刻之后紧接着是COR预清洁，随后进行外延沉积以填充凹部。 在外延沉积工艺期间，沉积的材料被掺杂以形成原位掺杂的光晕，然后切换掺杂剂以形成邻近光晕的原位掺杂的源极/漏极延伸。 或者，在形成原位掺杂的光晕之后，进行沉积工艺而没有掺杂剂，并且使用注入来形成源极/漏极延伸部。