Invention Grant
- Patent Title: Method of processing semiconductor wafer
- Patent Title (中): 半导体晶片的处理方法
-
Application No.: US12199547Application Date: 2008-08-27
-
Publication No.: US07902053B2Publication Date: 2011-03-08
- Inventor: Hiroyasu Ishida , Yasuyuki Sayama
- Applicant: Hiroyasu Ishida , Yasuyuki Sayama
- Applicant Address: JP Osaka JP Gunma
- Assignee: Sanyo Electric Co., Ltd,Sanyo Semiconductor Co., Ltd
- Current Assignee: Sanyo Electric Co., Ltd,Sanyo Semiconductor Co., Ltd
- Current Assignee Address: JP Osaka JP Gunma
- Agency: Morrison & Foerster LLP
- Priority: JP2007-238290 20070913
- Main IPC: H01L21/20
- IPC: H01L21/20

Abstract:
Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.
Public/Granted literature
- US20090075461A1 METHOD OF PROCESSING SEMICONDUCTOR WAFER Public/Granted day:2009-03-19
Information query
IPC分类: